Commit b0c41e96 authored by David S. Miller's avatar David S. Miller

Merge branch 'qed-Misc-fixes-in-the-interface-with-the-MFW'

Tomer Tayar says:

====================
qed: Misc fixes in the interface with the MFW

This patch series fixes several issues in the driver's interface with the
management FW (MFW).

v1->v2:
- Fix loop counter decrement to be pre instead of post.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 9c86336c b310974e
This diff is collapsed.
...@@ -635,11 +635,14 @@ struct qed_mcp_info { ...@@ -635,11 +635,14 @@ struct qed_mcp_info {
*/ */
spinlock_t cmd_lock; spinlock_t cmd_lock;
/* Flag to indicate whether sending a MFW mailbox command is blocked */
bool b_block_cmd;
/* Spinlock used for syncing SW link-changes and link-changes /* Spinlock used for syncing SW link-changes and link-changes
* originating from attention context. * originating from attention context.
*/ */
spinlock_t link_lock; spinlock_t link_lock;
bool block_mb_sending;
u32 public_base; u32 public_base;
u32 drv_mb_addr; u32 drv_mb_addr;
u32 mfw_mb_addr; u32 mfw_mb_addr;
...@@ -660,14 +663,20 @@ struct qed_mcp_info { ...@@ -660,14 +663,20 @@ struct qed_mcp_info {
}; };
struct qed_mcp_mb_params { struct qed_mcp_mb_params {
u32 cmd; u32 cmd;
u32 param; u32 param;
void *p_data_src; void *p_data_src;
u8 data_src_size; void *p_data_dst;
void *p_data_dst; u8 data_src_size;
u8 data_dst_size; u8 data_dst_size;
u32 mcp_resp; u32 mcp_resp;
u32 mcp_param; u32 mcp_param;
u32 flags;
#define QED_MB_FLAG_CAN_SLEEP (0x1 << 0)
#define QED_MB_FLAG_AVOID_BLOCK (0x1 << 1)
#define QED_MB_FLAGS_IS_SET(params, flag) \
({ typeof(params) __params = (params); \
(__params && (__params->flags & QED_MB_FLAG_ ## flag)); })
}; };
struct qed_drv_tlv_hdr { struct qed_drv_tlv_hdr {
......
...@@ -562,8 +562,10 @@ ...@@ -562,8 +562,10 @@
0 0
#define MCP_REG_CPU_STATE \ #define MCP_REG_CPU_STATE \
0xe05004UL 0xe05004UL
#define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)
#define MCP_REG_CPU_EVENT_MASK \ #define MCP_REG_CPU_EVENT_MASK \
0xe05008UL 0xe05008UL
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL
#define PGLUE_B_REG_PF_BAR0_SIZE \ #define PGLUE_B_REG_PF_BAR0_SIZE \
0x2aae60UL 0x2aae60UL
#define PGLUE_B_REG_PF_BAR1_SIZE \ #define PGLUE_B_REG_PF_BAR1_SIZE \
......
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