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Commit b0e99957 authored by David Woodhouse's avatar David Woodhouse
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PPC: Add support for ADS8272 board. 

From Kumar Gala <kumar.gala@motorola.com>
parent 57336024
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Showing with 860 additions and 13 deletions
arch/ppc/8260_io/fcc_enet.c
View file @ b0e99957
......@@ -159,20 +159,23 @@ static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
#ifdef CONFIG_SBC82xx
/* rx is clk9, tx is clk10
*/
/* rx is clk9, tx is clk10 */
#define PC_F1RXCLK ((uint)0x00000100)
#define PC_F1TXCLK ((uint)0x00000200)
#define CMX1_CLK_ROUTE ((uint)0x25000000)
#define CMX1_CLK_MASK ((uint)0xff000000)
#else
/* CLK12 is receive, CLK11 is transmit. These are board specific.
*/
#elif defined(CONFIG_ADS8272)
#define PC_F1RXCLK ((uint)0x00000400)
#define PC_F1TXCLK ((uint)0x00000200)
#define CMX1_CLK_ROUTE ((uint)0x36000000)
#define CMX1_CLK_MASK ((uint)0xff000000)
#else /* other boards */
/* CLK12 is receive, CLK11 is transmit. These are board specific. */
#define PC_F1RXCLK ((uint)0x00000800)
#define PC_F1TXCLK ((uint)0x00000400)
#define CMX1_CLK_ROUTE ((uint)0x3e000000)
#define CMX1_CLK_MASK ((uint)0xff000000)
#endif /* !CONFIG_SBC82xx */
#endif
/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
* but there is little variation among the choices.
......@@ -193,10 +196,17 @@ static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
/* CLK13 is receive, CLK14 is transmit. These are board dependent.
*/
#ifdef CONFIG_ADS8272
#define PC_F2RXCLK ((uint)0x00004000)
#define PC_F2TXCLK ((uint)0x00008000)
#define CMX2_CLK_ROUTE ((uint)0x00370000)
#define CMX2_CLK_MASK ((uint)0x00ff0000)
#else
#define PC_F2RXCLK ((uint)0x00001000)
#define PC_F2TXCLK ((uint)0x00002000)
#define CMX2_CLK_ROUTE ((uint)0x00250000)
#define CMX2_CLK_MASK ((uint)0x00ff0000)
#endif
/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
* but there is little variation among the choices.
......@@ -228,6 +238,9 @@ static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
/* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
#define PC_MDIO ((uint)0x00000002)
#define PC_MDCK ((uint)0x00000001)
#elif defined(CONFIG_ADS8272)
#define PC_MDIO ((uint)0x00002000)
#define PC_MDCK ((uint)0x00001000)
#else
#define PC_MDIO ((uint)0x00000004)
#define PC_MDCK ((uint)0x00000020)
......@@ -255,7 +268,7 @@ static fcc_info_t fcc_ports[] = {
#ifdef CONFIG_FCC1_ENET
{ 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
(PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
# if defined(CONFIG_TQM8260)
# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
PC_MDIO, PC_MDCK },
# else
0x00000004, 0x00000100 },
......@@ -264,7 +277,7 @@ static fcc_info_t fcc_ports[] = {
#ifdef CONFIG_FCC2_ENET
{ 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
(PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
# if defined(CONFIG_TQM8260)
# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
PC_MDIO, PC_MDCK },
# elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
0x00400000, 0x00200000 },
......@@ -275,7 +288,7 @@ static fcc_info_t fcc_ports[] = {
#ifdef CONFIG_FCC3_ENET
{ 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
(PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
# if defined(CONFIG_TQM8260)
# if defined(CONFIG_TQM8260) || defined(CONFIG_ADS8272)
PC_MDIO, PC_MDCK },
# else
0x00000001, 0x00000040 },
......@@ -1052,6 +1065,75 @@ static phy_info_t phy_info_qs6612 = {
#endif /* CONFIG_FEC_QS6612 */
/* ------------------------------------------------------------------------- */
/* The Davicom DM9131 is used on the HYMOD board */
#ifdef CONFIG_FCC_DM9131
/* register definitions */
#define MII_DM9131_ACR 16 /* Aux. Config Register */
#define MII_DM9131_ACSR 17 /* Aux. Config/Status Register */
#define MII_DM9131_10TCSR 18 /* 10BaseT Config/Status Reg. */
#define MII_DM9131_INTR 21 /* Interrupt Register */
#define MII_DM9131_RECR 22 /* Receive Error Counter Reg. */
#define MII_DM9131_DISCR 23 /* Disconnect Counter Register */
static void mii_parse_dm9131_acsr(uint mii_reg, struct net_device *dev)
{
volatile struct fcc_enet_private *fep = dev->priv;
uint s = fep->phy_status;
s &= ~(PHY_STAT_SPMASK);
switch ((mii_reg >> 12) & 0xf) {
case 1: s |= PHY_STAT_10HDX; break;
case 2: s |= PHY_STAT_10FDX; break;
case 4: s |= PHY_STAT_100HDX; break;
case 8: s |= PHY_STAT_100FDX; break;
}
fep->phy_status = s;
}
static phy_info_t phy_info_dm9131 = {
0x00181b80,
"DM9131",
(const phy_cmd_t []) { /* config */
/* parse cr and anar to get some info */
{ mk_mii_read(MII_REG_CR), mii_parse_cr },
{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
{ mk_mii_end, }
},
(const phy_cmd_t []) { /* startup - enable interrupts */
{ mk_mii_write(MII_DM9131_INTR, 0x0002), NULL },
{ mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
{ mk_mii_end, }
},
(const phy_cmd_t []) { /* ack_int */
/* we need to read INTR, SR and ANER to acknowledge */
{ mk_mii_read(MII_DM9131_INTR), NULL },
{ mk_mii_read(MII_REG_SR), mii_parse_sr },
{ mk_mii_read(MII_REG_ANER), NULL },
/* read acsr to get info */
{ mk_mii_read(MII_DM9131_ACSR), mii_parse_dm9131_acsr },
{ mk_mii_end, }
},
(const phy_cmd_t []) { /* shutdown - disable interrupts */
{ mk_mii_write(MII_DM9131_INTR, 0x0f00), NULL },
{ mk_mii_end, }
},
};
#endif /* CONFIG_FEC_DM9131 */
static phy_info_t *phy_info[] = {
#ifdef CONFIG_FCC_LXT970
......@@ -1064,7 +1146,11 @@ static phy_info_t *phy_info[] = {
#ifdef CONFIG_FCC_QS6612
&phy_info_qs6612,
#endif /* CONFIG_FEC_LXT971 */
#endif /* CONFIG_FEC_QS6612 */
#ifdef CONFIG_FCC_DM9131
&phy_info_dm9131,
#endif /* CONFIG_FEC_DM9131 */
NULL
};
......@@ -1773,11 +1859,11 @@ init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
*/
fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
#ifdef CONFIG_ADS8260
#ifdef CONFIG_PQ2ADS
/* Enable the PHY.
*/
ads_csr_addr[1] |= BCSR1_FETH_RST; /* Remove reset */
ads_csr_addr[1] &= ~BCSR1_FETHIEN; /* Enable */
*(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_FETHIEN;
*(volatile uint *)(BCSR_ADDR + 4) |= BCSR1_FETH_RST;
#endif
#if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260)
......
arch/ppc/Kconfig
View file @ b0e99957
......@@ -569,8 +569,16 @@ config TQM8260
End of Life: not yet :-)
URL: <http://www.denx.de/PDF/TQM82xx_SPEC_Rev005.pdf>
config ADS8272
bool "ADS8272"
endchoice
config PQ2ADS
bool
depends on ADS8272
default y
config TQM8xxL
bool
depends on 8xx && (TQM823L || TQM850L || FPS850L || TQM855L || TQM860L || SM850)
......@@ -590,6 +598,15 @@ config 8260
this option means that you wish to build a kernel for a machine with
an 8260 class CPU.
config 8272
bool
depends on 6xx
default y if ADS8272
select 8260
help
The MPC8272 CPM has a different internal dpram setup than other CPM2
devices
config CPM2
bool
depends on 8260
......
arch/ppc/configs/ads8272_defconfig 0 → 100644
View file @ b0e99957
This diff is collapsed.
arch/ppc/platforms/Makefile
View file @ b0e99957
......@@ -30,6 +30,7 @@ obj-$(CONFIG_PPC_RTAS) += error_log.o proc_rtas.o
obj-$(CONFIG_PREP_RESIDUAL) += residual.o
obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o
obj-$(CONFIG_EST8260) += est8260_setup.o
obj-$(CONFIG_PQ2ADS) += pq2ads_setup.o
obj-$(CONFIG_TQM8260) += tqm8260_setup.o
obj-$(CONFIG_EV64260) += ev64260_setup.o
obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o
......
arch/ppc/platforms/pq2ads.h 0 → 100644
View file @ b0e99957
/*
* A collection of structures, addresses, and values associated with
* the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
* Copied from the RPX-Classic and SBS8260 stuff.
*
* Copyright (c) 2001 Dan Malek (dan@mvista.com)
*/
#ifdef __KERNEL__
#ifndef __MACH_ADS8260_DEFS
#define __MACH_ADS8260_DEFS
#include <linux/config.h>
#include <asm/ppcboot.h>
/* Memory map is configured by the PROM startup.
* We just map a few things we need. The CSR is actually 4 byte-wide
* registers that can be accessed as 8-, 16-, or 32-bit values.
*/
#define CPM_MAP_ADDR ((uint)0xf0000000)
#define BCSR_ADDR ((uint)0xf4500000)
#define BCSR_SIZE ((uint)(32 * 1024))
#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
* only on word boundaries.
* Not all are used (yet), or are interesting to us (yet).
*/
/* Things of interest in the CSR.
*/
#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */
#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */
#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */
#define PHY_INTERRUPT SIU_INT_IRQ7
#ifdef CONFIG_PCI
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
#define PIRQA (NR_SIU_INTS + 0)
#define PIRQB (NR_SIU_INTS + 1)
#define PIRQC (NR_SIU_INTS + 2)
#define PIRQD (NR_SIU_INTS + 3)
/*
* PCI memory map definitions for MPC8266ADS-PCI.
*
* processor view
* local address PCI address target
* 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
* 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
* 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
*
* PCI master view
* local address PCI address target
* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
*/
/* window for a PCI master to access MPC8266 memory */
#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
/* window for the processor to access PCI memory with prefetching */
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
/* window for the processor to access PCI memory without prefetching */
#define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
#define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
/* window for the processor to access PCI I/O */
#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
#define _IO_BASE PCI_MSTR_IO_LOCAL
#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
#define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
#endif /* CONFIG_PCI */
#endif /* __MACH_ADS8260_DEFS */
#endif /* __KERNEL__ */
arch/ppc/platforms/pq2ads_setup.c 0 → 100644
View file @ b0e99957
/*
* arch/ppc/platforms/pq2ads_setup.c
*
* PQ2ADS platform support
*
* Author: Kumar Gala <kumar.gala@motorola.com>
* Derived from: est8260_setup.c by Allen Curtis
*
* Copyright 2004 Motorola Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <linux/seq_file.h>
#include <asm/mpc8260.h>
#include <asm/machdep.h>
static void (*callback_setup_arch)(void);
extern unsigned char __res[sizeof(bd_t)];
extern void m8260_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7);
static int
pq2ads_show_cpuinfo(struct seq_file *m)
{
bd_t *binfo = (bd_t *)__res;
seq_printf(m, "vendor\t\t: Motorola\n"
"machine\t\t: PQ2 ADS PowerPC\n"
"\n"
"mem size\t\t: 0x%08lx\n"
"console baud\t\t: %ld\n"
"\n",
binfo->bi_memsize,
binfo->bi_baudrate);
return 0;
}
static void __init
pq2ads_setup_arch(void)
{
printk("PQ2 ADS Port\n");
callback_setup_arch();
*(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_RS232_EN2;
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
/* Generic 8260 platform initialization */
m8260_init(r3, r4, r5, r6, r7);
/* Anything special for this platform */
ppc_md.show_cpuinfo = pq2ads_show_cpuinfo;
callback_setup_arch = ppc_md.setup_arch;
ppc_md.setup_arch = pq2ads_setup_arch;
}
include/asm-ppc/mpc8260.h
View file @ b0e99957
......@@ -36,6 +36,10 @@
#include <platforms/tqm8260.h>
#endif
#ifdef CONFIG_PQ2ADS
#include <platforms/pq2ads.h>
#endif
/* Make sure the memory translation stuff is there if PCI not used.
*/
#ifndef _IO_BASE
......
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