Commit b22ab733 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher

drm/amd/display/dm: add picasso support

Add support for picasso to the display manager.
Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5f4e2085
...@@ -2177,6 +2177,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) ...@@ -2177,6 +2177,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
case CHIP_VEGA20: case CHIP_VEGA20:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
#endif #endif
return amdgpu_dc != 0; return amdgpu_dc != 0;
#endif #endif
......
...@@ -1213,7 +1213,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) ...@@ -1213,7 +1213,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
if (adev->asic_type == CHIP_VEGA10 || if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_RAVEN) adev->asic_type == CHIP_RAVEN ||
adev->asic_type == CHIP_PICASSO)
client_id = SOC15_IH_CLIENTID_DCE; client_id = SOC15_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
...@@ -1632,6 +1633,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) ...@@ -1632,6 +1633,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break; break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
if (dcn10_register_irq_handlers(dm->adev)) { if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n"); DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail; goto fail;
...@@ -1858,6 +1860,7 @@ static int dm_early_init(void *handle) ...@@ -1858,6 +1860,7 @@ static int dm_early_init(void *handle)
break; break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
adev->mode_info.num_crtc = 4; adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4; adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4; adev->mode_info.num_dig = 4;
...@@ -2106,7 +2109,8 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, ...@@ -2106,7 +2109,8 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
if (adev->asic_type == CHIP_VEGA10 || if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_RAVEN) { adev->asic_type == CHIP_RAVEN ||
adev->asic_type == CHIP_PICASSO) {
/* Fill GFX9 params */ /* Fill GFX9 params */
plane_state->tiling_info.gfx9.num_pipes = plane_state->tiling_info.gfx9.num_pipes =
adev->gfx.config.gb_addr_config_fields.num_pipes; adev->gfx.config.gb_addr_config_fields.num_pipes;
......
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