Commit b32eaf48 authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://bk.arm.linux.org.uk/linux-2.5-rmk

into home.transmeta.com:/home/torvalds/v2.5/linux
parents f5bdbdbf f8269e32
...@@ -35,7 +35,7 @@ __XScale_start: ...@@ -35,7 +35,7 @@ __XScale_start:
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_ARCH_IQ80321 #ifdef CONFIG_ARCH_IQ80321
orr pc, pc, #0xa0000000 orr pc, pc, #PHYS_OFFSET @ jump to physical memory if we are not there.
nop nop
mov r7, #MACH_TYPE_IQ80321 mov r7, #MACH_TYPE_IQ80321
#endif #endif
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* linux/arch/arm/kernel/process.c * linux/arch/arm/kernel/process.c
* *
* Copyright (C) 1996-2000 Russell King - Converted to ARM. * Copyright (C) 1996-2000 Russell King - Converted to ARM.
* Origional Copyright (C) 1995 Linus Torvalds * Original Copyright (C) 1995 Linus Torvalds
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
...@@ -212,13 +212,13 @@ int iop321_setup(int nr, struct pci_sys_data *sys) ...@@ -212,13 +212,13 @@ int iop321_setup(int nr, struct pci_sys_data *sys)
switch (nr) { switch (nr) {
case 0: case 0:
res[0].start = IOP321_PCI_LOWER_IO + 0x6e000000; res[0].start = IOP321_PCI_IO_BASE + 0x6e000000;
res[0].end = IOP321_PCI_LOWER_IO + 0x6e00ffff; res[0].end = IOP321_PCI_IO_BASE + IOP321_PCI_IO_SIZE-1 + 0x6e000000;
res[0].name = "PCI IO Primary"; res[0].name = "PCI IO Primary";
res[0].flags = IORESOURCE_IO; res[0].flags = IORESOURCE_IO;
res[1].start = IOP321_PCI_LOWER_MEM; res[1].start = IOP321_PCI_MEM_BASE;
res[1].end = IOP321_PCI_LOWER_MEM + IOP321_PCI_WINDOW_SIZE; res[1].end = IOP321_PCI_MEM_BASE + IOP321_PCI_MEM_SIZE;
res[1].name = "PCI Memory Primary"; res[1].name = "PCI Memory Primary";
res[1].flags = IORESOURCE_MEM; res[1].flags = IORESOURCE_MEM;
break; break;
......
...@@ -101,7 +101,7 @@ static void iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) ...@@ -101,7 +101,7 @@ static void iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
* *
* Since the timer interrupt is cascaded through the CPLD and * Since the timer interrupt is cascaded through the CPLD and
* the 80312 and the demux code calls do_IRQ, the irq count is * the 80312 and the demux code calls do_IRQ, the irq count is
* going to be atleast 2 when we get here and this will cause the * going to be at least 2 when we get here and this will cause the
* kernel to increment the system tick counter even if we're * kernel to increment the system tick counter even if we're
* idle. This causes it to look like there's always 100% system * idle. This causes it to look like there's always 100% system
* time, which is not the case. To get around it, we just decrement * time, which is not the case. To get around it, we just decrement
......
/* /*
* linux/arch/arm/mach-iop3xx/mm.c * linux/arch/arm/mach-iop3xx/mm.c
* *
* Low level memory intialization for IOP321 based systems * Low level memory initialization for IOP321 based systems
* *
* Author: Rory Bolt <rorybolt@pacbell.net> * Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt * Copyright (C) 2002 Rory Bolt
...@@ -31,7 +31,7 @@ static struct map_desc iop80321_std_desc[] __initdata = { ...@@ -31,7 +31,7 @@ static struct map_desc iop80321_std_desc[] __initdata = {
/* virtual physical length type */ /* virtual physical length type */
/* mem mapped registers */ /* mem mapped registers */
{ 0xfff00000, 0xffffe000, 0x00002000, MT_DEVICE }, { IOP321_VIRT_MEM_BASE, IOP321_PHY_MEM_BASE, 0x00002000, MT_DEVICE },
/* PCI IO space */ /* PCI IO space */
{ 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE } { 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
...@@ -52,7 +52,7 @@ static struct map_desc iq80321_io_desc[] __initdata = { ...@@ -52,7 +52,7 @@ static struct map_desc iq80321_io_desc[] __initdata = {
/* virtual physical length type */ /* virtual physical length type */
/* on-board devices */ /* on-board devices */
{ 0xfe800000, 0xfe800000, 0x00100000, MT_DEVICE } { 0xfe800000, IQ80321_UART1, 0x00100000, MT_DEVICE }
}; };
void __init iq80321_map_io(void) void __init iq80321_map_io(void)
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
* *
* Since this file should be linked before any other machine specific file, * Since this file should be linked before any other machine specific file,
* the __initcall() here will be executed first. This serves as default * the __initcall() here will be executed first. This serves as default
* initialization stuff for PXA machines which can be overriden later if * initialization stuff for PXA machines which can be overridden later if
* need be. * need be.
*/ */
#include <linux/config.h> #include <linux/config.h>
......
...@@ -95,7 +95,7 @@ ENTRY(pxa_cpu_suspend) ...@@ -95,7 +95,7 @@ ENTRY(pxa_cpu_suspend)
* This is to allow sleep_save_sp to be accessed with a relative load * This is to allow sleep_save_sp to be accessed with a relative load
* while we can't rely on any MMU translation. We could have put * while we can't rely on any MMU translation. We could have put
* sleep_save_sp in the .text section as well, but some setups might * sleep_save_sp in the .text section as well, but some setups might
* insist on it to be truely read-only. * insist on it to be truly read-only.
*/ */
.data .data
......
...@@ -171,7 +171,7 @@ sa1110_sdram_controller_fix: ...@@ -171,7 +171,7 @@ sa1110_sdram_controller_fix:
* This is to allow sleep_save_sp to be accessed with a relative load * This is to allow sleep_save_sp to be accessed with a relative load
* while we can't rely on any MMU translation. We could have put * while we can't rely on any MMU translation. We could have put
* sleep_save_sp in the .text section as well, but some setups might * sleep_save_sp in the .text section as well, but some setups might
* insist on it to be truely read-only. * insist on it to be truly read-only.
*/ */
.data .data
......
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
#endif #endif
/* /*
* Our node_data structure for discontigous memory. * Our node_data structure for discontiguous memory.
*/ */
static bootmem_data_t node_bootmem_data[NR_NODES]; static bootmem_data_t node_bootmem_data[NR_NODES];
......
...@@ -4,6 +4,6 @@ ...@@ -4,6 +4,6 @@
*/ */
/* /*
* No on board timer, implemenation @ arch/arm/kernel/xscale-time.c * No on board timer, implementation @ arch/arm/kernel/xscale-time.c
*/ */
...@@ -95,7 +95,7 @@ ...@@ -95,7 +95,7 @@
* Because of the wide memory address space between physical RAM banks on the * Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much more convenient to use Linux's NUMA support to implement * SA1100, it's much more convenient to use Linux's NUMA support to implement
* our memory map representation. Assuming all memory nodes have equal access * our memory map representation. Assuming all memory nodes have equal access
* characteristics, we then have generic discontigous memory support. * characteristics, we then have generic discontiguous memory support.
* *
* Of course, all this isn't mandatory for SA1100 implementations with only * Of course, all this isn't mandatory for SA1100 implementations with only
* one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM.
......
...@@ -55,7 +55,7 @@ typedef struct buf_desc ...@@ -55,7 +55,7 @@ typedef struct buf_desc
#define ETHER_ARC_SIZE (21) #define ETHER_ARC_SIZE (21)
/* /*
* Regsiter definitions and masks * Register definitions and masks
*/ */
#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) #define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100))
#define ETHER_DMA_CTL_DMBURST_OFST (2) #define ETHER_DMA_CTL_DMBURST_OFST (2)
......
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
/* /*
* *
* This file contains the register definitions for the Excalibur * This file contains the register definitions for the Excalibur
* Interrupnt controller INT_CTRL00. * Interrupt controller INT_CTRL00.
* *
* Copyright (C) 2001 Altera Corporation * Copyright (C) 2001 Altera Corporation
* *
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
/* DO NOT EDIT!! - this file automatically generated /* DO NOT EDIT!! - this file automatically generated
* from .s file by awk -f s2h.awk * from .s file by awk -f s2h.awk
*/ */
/* Bit field defintions /* Bit field definitions
* Copyright (C) ARM Limited 1998. All rights reserved. * Copyright (C) ARM Limited 1998. All rights reserved.
*/ */
......
/* /*
* linux/include/asm/arch-iop3xx/iop310.h * linux/include/asm/arch-iop3xx/iop310.h
* *
* Intel IOP310 Compainion Chip definitions * Intel IOP310 Companion Chip definitions
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
......
...@@ -17,12 +17,10 @@ ...@@ -17,12 +17,10 @@
/* /*
* IOP321 I/O and Mem space regions for PCI autoconfiguration * IOP321 I/O and Mem space regions for PCI autoconfiguration
*/ */
#define IOP321_PCI_LOWER_IO 0x90000000 #define IOP321_PCI_IO_BASE 0x90000000
#define IOP321_PCI_UPPER_IO 0x9000ffff #define IOP321_PCI_IO_SIZE 0x00010000
#define IOP321_PCI_LOWER_MEM 0x80000000 #define IOP321_PCI_MEM_BASE 0x40000000
#define IOP321_PCI_UPPER_MEM 0x83ffffff #define IOP321_PCI_MEM_SIZE 0x40000000
#define IOP321_PCI_WINDOW_SIZE 64 * 0x100000
/* /*
* IOP321 chipset registers * IOP321 chipset registers
......
...@@ -690,9 +690,9 @@ typedef void (*ExcpHndlr) (void) ; ...@@ -690,9 +690,9 @@ typedef void (*ExcpHndlr) (void) ;
#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
#define ICCR0_AME (1 << 7) /* Adress match enable */ #define ICCR0_AME (1 << 7) /* Address match enable */
#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ #define ICCR0_RIE (1 << 5) /* Receive FIFO interrupt enable */
#define ICCR0_RXE (1 << 4) /* Receive enable */ #define ICCR0_RXE (1 << 4) /* Receive enable */
#define ICCR0_TXE (1 << 3) /* Transmit enable */ #define ICCR0_TXE (1 << 3) /* Transmit enable */
#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
......
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
#define _ADS_UARTC 0x10140000 /* UART C */ #define _ADS_UARTC 0x10140000 /* UART C */
#define _ADS_UARTD 0x10160000 /* UART D */ #define _ADS_UARTD 0x10160000 /* UART D */
/* UART controll lines GPIOs */ /* UART control lines GPIOs */
#define GPIO_GC_UART0_RTS GPIO_GPIO15 #define GPIO_GC_UART0_RTS GPIO_GPIO15
#define GPIO_GC_UART1_RTS GPIO_GPIO17 #define GPIO_GC_UART1_RTS GPIO_GPIO17
#define GPIO_GC_UART2_RTS GPIO_GPIO19 #define GPIO_GC_UART2_RTS GPIO_GPIO19
...@@ -71,7 +71,7 @@ ...@@ -71,7 +71,7 @@
#define GPIO_GC_UART1_CTS GPIO_GPIO16 #define GPIO_GC_UART1_CTS GPIO_GPIO16
#define GPIO_GC_UART2_CTS GPIO_GPIO17 #define GPIO_GC_UART2_CTS GPIO_GPIO17
/* UART controll lines IRQs */ /* UART control lines IRQs */
#define IRQ_GC_UART0_CTS IRQ_GPIO14 #define IRQ_GC_UART0_CTS IRQ_GPIO14
#define IRQ_GC_UART1_CTS IRQ_GPIO16 #define IRQ_GC_UART1_CTS IRQ_GPIO16
#define IRQ_GC_UART2_CTS IRQ_GPIO17 #define IRQ_GC_UART2_CTS IRQ_GPIO17
......
...@@ -480,7 +480,7 @@ ...@@ -480,7 +480,7 @@
#define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ #define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */
#define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ #define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */
#define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ #define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */
#define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:ouput in sleep mode */ #define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */
#define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ #define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */
#define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ #define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */
#define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ #define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */
......
...@@ -60,7 +60,7 @@ ...@@ -60,7 +60,7 @@
* Because of the wide memory address space between physical RAM banks on the * Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much convenient to use Linux's NUMA support to implement our * SA1100, it's much convenient to use Linux's NUMA support to implement our
* memory map representation. Assuming all memory nodes have equal access * memory map representation. Assuming all memory nodes have equal access
* characteristics, we then have generic discontigous memory support. * characteristics, we then have generic discontiguous memory support.
* *
* Of course, all this isn't mandatory for SA1100 implementations with only * Of course, all this isn't mandatory for SA1100 implementations with only
* one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM.
......
...@@ -32,7 +32,7 @@ static void puts( const char *s ) ...@@ -32,7 +32,7 @@ static void puts( const char *s )
} while (0); } while (0);
for (; *s; s++) { for (; *s; s++) {
/* wait for space in the UART's transmiter */ /* wait for space in the UART's transmitter */
while (!(UART(UTSR1) & UTSR1_TNF)); while (!(UART(UTSR1) & UTSR1_TNF));
/* send the character out. */ /* send the character out. */
......
...@@ -182,7 +182,7 @@ dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size, ...@@ -182,7 +182,7 @@ dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
* @dir: DMA transfer direction * @dir: DMA transfer direction
* *
* Map a set of buffers described by scatterlist in streaming * Map a set of buffers described by scatterlist in streaming
* mode for DMA. This is the scather-gather version of the * mode for DMA. This is the scatter-gather version of the
* above pci_map_single interface. Here the scatter gather list * above pci_map_single interface. Here the scatter gather list
* elements are each tagged with the appropriate dma address * elements are each tagged with the appropriate dma address
* and length. They are obtained via sg_dma_{address,length}(SG). * and length. They are obtained via sg_dma_{address,length}(SG).
......
...@@ -37,7 +37,7 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) ...@@ -37,7 +37,7 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
/* /*
* We use the old 2.5.5-rmk1 hack for this. * We use the old 2.5.5-rmk1 hack for this.
* This is not truely correct, but should be functional. * This is not truly correct, but should be functional.
*/ */
#define pte_alloc_one(mm,addr) ((struct page *)pte_alloc_one_kernel(mm,addr)) #define pte_alloc_one(mm,addr) ((struct page *)pte_alloc_one_kernel(mm,addr))
#define pte_free(pte) pte_free_kernel((pte_t *)pte) #define pte_free(pte) pte_free_kernel((pte_t *)pte)
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
/* DO NOT EDIT!! - this file automatically generated /* DO NOT EDIT!! - this file automatically generated
* from .s file by awk -f s2h.awk * from .s file by awk -f s2h.awk
*/ */
/* Size defintions /* Size definitions
* Copyright (C) ARM Limited 1998. All rights reserved. * Copyright (C) ARM Limited 1998. All rights reserved.
*/ */
......
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