Commit b37e1613 authored by Rojhalat Ibrahim's avatar Rojhalat Ibrahim Committed by Scott Wood

powerpc/pci: Fix boot panic on mpc83xx (regression)

The following commit caused a fatal oops when booting on mpc83xx with
a non-express PCI bus (regardless of whether a PCI device is present):

commit 50d8f87d
Author: Rojhalat Ibrahim <imr@rtschenk.de>
Date:   Mon Apr 8 10:15:28 2013 +0200

    powerpc/fsl-pci Make PCIe hotplug work with Freescale PCIe controllers

    Up to now the PCIe link status on Freescale PCIe controllers was only
    checked once at boot time. So hotplug did not work. With this patch the
    link status is checked on every config read. PCIe devices not present at
    boot time are found after doing 'echo 1 >/sys/bus/pci/rescan'.
Signed-off-by: default avatarRojhalat Ibrahim <imr@rtschenk.de>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>

This patch fixes the issue by calling setup_indirect_pci for all device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe controllers.
Reported-by: default avatarMichael Guntsche <mike@it-loops.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: default avatarRojhalat Ibrahim <imr@rtschenk.de>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 17858ca6
...@@ -97,22 +97,14 @@ static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, ...@@ -97,22 +97,14 @@ static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
return indirect_read_config(bus, devfn, offset, len, val); return indirect_read_config(bus, devfn, offset, len, val);
} }
static struct pci_ops fsl_indirect_pci_ops = #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
static struct pci_ops fsl_indirect_pcie_ops =
{ {
.read = fsl_indirect_read_config, .read = fsl_indirect_read_config,
.write = indirect_write_config, .write = indirect_write_config,
}; };
static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags)
{
setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
hose->ops = &fsl_indirect_pci_ops;
}
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40 #define MAX_PHYS_ADDR_BITS 40
static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
...@@ -504,13 +496,15 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) ...@@ -504,13 +496,15 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
if (!hose->private_data) if (!hose->private_data)
goto no_bridge; goto no_bridge;
fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN); PPC_INDIRECT_TYPE_BIG_ENDIAN);
if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
/* use fsl_indirect_read_config for PCIe */
hose->ops = &fsl_indirect_pcie_ops;
/* For PCIE read HEADER_TYPE to identify controler mode */ /* For PCIE read HEADER_TYPE to identify controler mode */
early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
...@@ -814,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) ...@@ -814,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
if (ret) if (ret)
goto err0; goto err0;
} else { } else {
fsl_setup_indirect_pci(hose, rsrc_cfg.start, setup_indirect_pci(hose, rsrc_cfg.start,
rsrc_cfg.start + 4, 0); rsrc_cfg.start + 4, 0);
} }
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
......
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