Commit b4bcfccb authored by Chris Packham's avatar Chris Packham Committed by Gregory CLEMENT

ARM: dts: mvebu: Move mv98dx3236 clock bindings

Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.

Moving the binding to the DFX block enables support for different clock
strapping options in hardware.
Signed-off-by: default avatarChris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 43e28ba8
...@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x: ...@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x:
4 = dclk (SDRAM Interface Clock) 4 = dclk (SDRAM Interface Clock)
5 = refclk (Reference Clock) 5 = refclk (Reference Clock)
The following is a list of provided IDs and clock names on 98dx3236:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = ddrclk (DDR clock)
3 = mpll (MPLL Clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove: The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock) 0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock) 1 = cpuclk (CPU0 clock)
...@@ -49,6 +55,7 @@ Required properties: ...@@ -49,6 +55,7 @@ Required properties:
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
"marvell,dove-core-clock" - for Dove SoC core clocks "marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
......
...@@ -119,6 +119,16 @@ ID Clock Peripheral ...@@ -119,6 +119,16 @@ ID Clock Peripheral
29 sata1lnk 29 sata1lnk
30 sata1 SATA Host 1 30 sata1 SATA Host 1
The following is a list of provided IDs for 98dx3236:
ID Clock Peripheral
-----------------------------------
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
17 sdio SDHCI Host
18 usb0 USB Host 0
22 xor0 XOR DMA 0
The following is a list of provided IDs for Dove: The following is a list of provided IDs for Dove:
ID Clock Peripheral ID Clock Peripheral
----------------------------------- -----------------------------------
...@@ -169,6 +179,7 @@ Required properties: ...@@ -169,6 +179,7 @@ Required properties:
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
"marvell,dove-gating-clock" - for Dove SoC clock gating "marvell,dove-gating-clock" - for Dove SoC clock gating
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
- reg : shall be the register address of the Clock Gating Control register - reg : shall be the register address of the Clock Gating Control register
......
...@@ -176,18 +176,12 @@ systemc: system-controller@18200 { ...@@ -176,18 +176,12 @@ systemc: system-controller@18200 {
}; };
gateclk: clock-gating-control@18220 { gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-xp-gating-clock"; compatible = "marvell,mv98dx3236-gating-clock";
reg = <0x18220 0x4>; reg = <0x18220 0x4>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
coreclk: mvebu-sar@18230 {
compatible = "marvell,mv98dx3236-core-clock";
reg = <0x18230 0x08>;
#clock-cells = <1>;
};
cpuclk: clock-complex@18700 { cpuclk: clock-complex@18700 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "marvell,mv98dx3236-cpu-clock"; compatible = "marvell,mv98dx3236-cpu-clock";
...@@ -264,6 +258,12 @@ dfx: dfx-server@ac000000 { ...@@ -264,6 +258,12 @@ dfx: dfx-server@ac000000 {
ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
reg = <MBUS_ID(0x08, 0x00) 0 0x100000>; reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
coreclk: mvebu-sar@f8204 {
compatible = "marvell,mv98dx3236-core-clock";
reg = <0xf8204 0x4>;
#clock-cells = <1>;
};
dfx_coredivclk: corediv-clock@f8268 { dfx_coredivclk: corediv-clock@f8268 {
compatible = "marvell,mv98dx3236-corediv-clock"; compatible = "marvell,mv98dx3236-corediv-clock";
reg = <0xf8268 0xc>; reg = <0xf8268 0xc>;
......
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