Commit b734735f authored by Christian Lütke-Stetzkamp's avatar Christian Lütke-Stetzkamp Committed by Greg Kroah-Hartman

staging: mt7621-mmc: Remove code for different soc types

Remove code that is intended for soc other then the mt7621 because
this driver is only for that soc. This also removes some conditions.
However the remaining code is also at the wrong place, it just selects
the mode of the pins, this is a job for pinctl not for the sdxc driver.
Signed-off-by: default avatarChristian Lütke-Stetzkamp <christian@lkamp.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b1619236
......@@ -2987,27 +2987,10 @@ static int __init mt_msdc_init(void)
printk("MTK MSDC device init.\n");
mtk_sd_device.dev.platform_data = &msdc0_hw;
if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
// Set the pins for sdxc to sdxc mode
//FIXME: this should be done by pinctl and not by the sd driver
reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
//#if defined (CONFIG_RALINK_MT7620)
if (ralink_soc == MT762X_SOC_MT7620A)
reg |= 0x1 << 18;
//#endif
} else {
//#elif defined (CONFIG_RALINK_MT7628)
/* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x3c));
reg |= 0x1e << 16;
sdr_write32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x3c), reg);
reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 10);
#if defined(CONFIG_MTK_MMC_EMMC_8BIT)
reg |= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
msdc0_hw.data_pins = 8,
#endif
//#endif
}
sdr_write32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60), reg);
//platform_device_register(&mtk_sd_device);
/* end of +++ */
......
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