Commit b74d1315 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo

perf vendor events: Add Broadwell V17 event file

Add a Intel event file for perf.

Committer note:

Testing it on a ThinkPad t450s:

  [acme@jouet linux]$ perf list
<SNIP>
  Cache:
    l1d.replacement
         [L1D data line replacements]
    l1d_pend_miss.fb_full
         [Cycles a demand request was blocked due to Fill Buffers inavailability]
    l1d_pend_miss.pending
         [L1D miss oustandings duration in cycles]
    l1d_pend_miss.pending_cycles
         [Cycles with L1D load Misses outstanding]
<SNIP>
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Tested-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-3qh7e0quf7qlttjoz250hfcl@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 27b565b1
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[
{
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100007",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
"EventCode": "0x63",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"CounterHTOff": "0,1,2,3,4,5,6,7"
}
]
\ No newline at end of file
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Family-model,Version,Filename,EventType Family-model,Version,Filename,EventType
GenuineIntel-6-56,v5,broadwellde,core GenuineIntel-6-56,v5,broadwellde,core
GenuineIntel-6-3D,v17,broadwell,core
GenuineIntel-6-47,v17,broadwell,core
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