Commit b7bbdbee authored by Chanho Park's avatar Chanho Park Committed by Kukjin Kim

ARM: EXYNOS: Enable PMUs for exynos4

This patch defines irq numbers of ARM performance monitoring unit for exynos4.
Firs of all, we need to fix IRQ_PMU correctly and to split pmu initialization
of exynos from plat-samsung for easily defining it.

The number of CPU cores and PMU irq numbers are vary according to soc types.
So, we need to identify each soc type using soc_is_xxx function and to define
the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and pmus.
Signed-off-by: default avatarChanho Park <chanho61.park@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 4e164dc5
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
#include <mach/regs-irq.h> #include <mach/regs-irq.h>
#include <mach/regs-pmu.h> #include <mach/regs-pmu.h>
#include <mach/regs-gpio.h> #include <mach/regs-gpio.h>
#include <mach/irqs.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
...@@ -850,3 +851,30 @@ static int __init exynos_init_irq_eint(void) ...@@ -850,3 +851,30 @@ static int __init exynos_init_irq_eint(void)
return 0; return 0;
} }
arch_initcall(exynos_init_irq_eint); arch_initcall(exynos_init_irq_eint);
static struct resource exynos4_pmu_resource[] = {
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
#if defined(CONFIG_SOC_EXYNOS4412)
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
#endif
};
static struct platform_device exynos4_device_pmu = {
.name = "arm-pmu",
.num_resources = ARRAY_SIZE(exynos4_pmu_resource),
.resource = exynos4_pmu_resource,
};
static int __init exynos_armpmu_init(void)
{
if (!of_have_populated_dt()) {
if (soc_is_exynos4210() || soc_is_exynos4212())
exynos4_device_pmu.num_resources = 2;
platform_device_register(&exynos4_device_pmu);
}
return 0;
}
arch_initcall(exynos_armpmu_init);
...@@ -126,7 +126,7 @@ ...@@ -126,7 +126,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107) #define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108) #define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109) #define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
#define EXYNOS4_IRQ_PMU IRQ_SPI(110) #define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPS IRQ_SPI(111) #define EXYNOS4_IRQ_GPS IRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) #define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113) #define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
...@@ -134,6 +134,11 @@ ...@@ -134,6 +134,11 @@
#define EXYNOS4_IRQ_TSI IRQ_SPI(115) #define EXYNOS4_IRQ_TSI IRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116) #define EXYNOS4_IRQ_SATA IRQ_SPI(116)
#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4) #define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4) #define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
...@@ -234,7 +239,6 @@ ...@@ -234,7 +239,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0 #define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD #define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
#define IRQ_PMU EXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO #define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC #define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
......
...@@ -1113,7 +1113,7 @@ struct platform_device s5p_device_onenand = { ...@@ -1113,7 +1113,7 @@ struct platform_device s5p_device_onenand = {
/* PMU */ /* PMU */
#ifdef CONFIG_PLAT_S5P #if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
static struct resource s5p_pmu_resource[] = { static struct resource s5p_pmu_resource[] = {
DEFINE_RES_IRQ(IRQ_PMU) DEFINE_RES_IRQ(IRQ_PMU)
}; };
......
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