Commit b916a609 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'mvebu-dt-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt

Pull "mvebu dt for 4.12 (part 1)" from Gregory CLEMENT:

- Add node lable for Armada 38x
- Add support for Synology DS116 NAS and Linksys WRT1900ACS
- Update mbus controller description on Armada 38x allowing entering in standby
- Add default trigger for sata led on various linksys boards
- Update newly added armada-xp-98dx3236
- Enable hardware buffer manager support for the devices in the
  Linksys WRT AC Serie

* tag 'mvebu-dt-4.12-1' of git://git.infradead.org/linux-mvebu:
  ARM: dts: mvebu: linksys: enable buffer manager support
  ARM: dts: mvebu: remove unnecessary PCI range from 98dx3236
  ARM: dts: mvebu: Move mv98dx3236 clock bindings
  ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
  ARM: dts: armada-xp-98dx3236: combine dfx server nodes
  ARM: dts: armada: Add default trigger for sata led
  ARM: dts: armada-38x: Adjust mbus controller description on Armada 38x
  ARM: dts: armada-385: add support for the Linksys WRT1900ACS (Shelby)
  ARM: dts: armada-385-synology-ds116: add support for Synology DS116 NAS
  ARM: dts: armada-38x add node labels
parents 2c5ad976 cd2f0d0d
...@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x: ...@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x:
4 = dclk (SDRAM Interface Clock) 4 = dclk (SDRAM Interface Clock)
5 = refclk (Reference Clock) 5 = refclk (Reference Clock)
The following is a list of provided IDs and clock names on 98dx3236:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = ddrclk (DDR clock)
3 = mpll (MPLL Clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove: The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock) 0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock) 1 = cpuclk (CPU0 clock)
...@@ -49,6 +55,7 @@ Required properties: ...@@ -49,6 +55,7 @@ Required properties:
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
"marvell,dove-core-clock" - for Dove SoC core clocks "marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
......
...@@ -119,6 +119,16 @@ ID Clock Peripheral ...@@ -119,6 +119,16 @@ ID Clock Peripheral
29 sata1lnk 29 sata1lnk
30 sata1 SATA Host 1 30 sata1 SATA Host 1
The following is a list of provided IDs for 98dx3236:
ID Clock Peripheral
-----------------------------------
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
17 sdio SDHCI Host
18 usb0 USB Host 0
22 xor0 XOR DMA 0
The following is a list of provided IDs for Dove: The following is a list of provided IDs for Dove:
ID Clock Peripheral ID Clock Peripheral
----------------------------------- -----------------------------------
...@@ -169,6 +179,7 @@ Required properties: ...@@ -169,6 +179,7 @@ Required properties:
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
"marvell,dove-gating-clock" - for Dove SoC clock gating "marvell,dove-gating-clock" - for Dove SoC clock gating
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
- reg : shall be the register address of the Clock Gating Control register - reg : shall be the register address of the Clock Gating Control register
......
...@@ -32,19 +32,16 @@ DFX Server bindings ...@@ -32,19 +32,16 @@ DFX Server bindings
------------------- -------------------
Required properties: Required properties:
- compatible: must be "marvell,dfx-server" - compatible: must be "marvell,dfx-server", "simple-bus"
- ranges: describes the address mapping of a memory-mapped bus.
- reg: address and length of the register set for the device. - reg: address and length of the register set for the device.
Example: Example:
dfx-registers { dfx-server {
compatible = "simple-bus"; compatible = "marvell,dfx-server", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
dfx: dfx@0 {
compatible = "marvell,dfx-server";
reg = <0 0x100000>;
};
}; };
...@@ -976,6 +976,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ ...@@ -976,6 +976,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \ armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \ armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \ armada-385-linksys-cobra.dtb \
armada-385-linksys-shelby.dtb \
armada-385-synology-ds116.dtb \
armada-385-turris-omnia.dtb \ armada-385-turris-omnia.dtb \
armada-388-clearfog.dtb \ armada-388-clearfog.dtb \
armada-388-clearfog-base.dtb \ armada-388-clearfog-base.dtb \
......
...@@ -109,6 +109,7 @@ power { ...@@ -109,6 +109,7 @@ power {
sata { sata {
label = "caiman:white:sata"; label = "caiman:white:sata";
linux,default-trigger = "disk-activity";
}; };
}; };
}; };
...@@ -109,6 +109,7 @@ power { ...@@ -109,6 +109,7 @@ power {
sata { sata {
label = "cobra:white:sata"; label = "cobra:white:sata";
linux,default-trigger = "disk-activity";
}; };
}; };
}; };
/*
* Device Tree file for the Linksys WRT1900ACS (Shelby)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT1900ACS";
compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs{
i2c@11000 {
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
wan_amber@0 {
label = "shelby:amber:wan";
reg = <0x0>;
};
wan_white@1 {
label = "shelby:white:wan";
reg = <0x1>;
};
wlan_2g@2 {
label = "shelby:white:wlan_2g";
reg = <0x2>;
};
wlan_5g@3 {
label = "shelby:white:wlan_5g";
reg = <0x3>;
};
usb2@5 {
label = "shelby:white:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "shelby:white:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "shelby:white:usb3_2";
reg = <0x7>;
};
wps_white@8 {
label = "shelby:white:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "shelby:amber:wps";
reg = <0x9>;
};
};
};
};
};
gpio-leds {
power {
label = "shelby:white:power";
};
sata {
label = "shelby:white:sata";
};
};
};
...@@ -59,7 +59,8 @@ soc { ...@@ -59,7 +59,8 @@ soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs { internal-regs {
i2c@11000 { i2c@11000 {
...@@ -88,6 +89,9 @@ serial@12000 { ...@@ -88,6 +89,9 @@ serial@12000 {
ethernet@70000 { ethernet@70000 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
fixed-link { fixed-link {
speed = <1000>; speed = <1000>;
full-duplex; full-duplex;
...@@ -97,6 +101,9 @@ fixed-link { ...@@ -97,6 +101,9 @@ fixed-link {
ethernet@34000 { ethernet@34000 {
status = "okay"; status = "okay";
phy-mode = "sgmii"; phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
fixed-link { fixed-link {
speed = <1000>; speed = <1000>;
full-duplex; full-duplex;
...@@ -159,6 +166,10 @@ sata@a8000 { ...@@ -159,6 +166,10 @@ sata@a8000 {
status = "okay"; status = "okay";
}; };
bm@c8000 {
status = "okay";
};
/* USB part of the eSATA/USB 2.0 port */ /* USB part of the eSATA/USB 2.0 port */
usb@58000 { usb@58000 {
status = "okay"; status = "okay";
...@@ -241,6 +252,10 @@ partition@180000 { ...@@ -241,6 +252,10 @@ partition@180000 {
}; };
}; };
bm-bppi {
status = "okay";
};
pcie-controller { pcie-controller {
status = "okay"; status = "okay";
......
/*
* Device Tree file for Synology DS116 NAS
*
* Copyright (C) 2017 Willy Tarreau <w@1wt.eu>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Synology DS116";
compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
i2c@11000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
serial@12000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
serial@12100 {
/* A PIC16F1829 is connected to uart1 at 9600 bps,
* and takes single-character orders :
* "1" : power off // already handled by the poweroff node
* "2" : short beep
* "3" : long beep
* "4" : turn the power LED ON
* "5" : flash the power LED
* "6" : turn the power LED OFF
* "7" : turn the status LED OFF
* "8" : turn the status LED ON
* "9" : flash the status LED
* "A" : flash the motherboard LED (D8)
* "B" : turn the motherboard LED OFF
* "C" : hard reset
*/
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
poweroff@12100 {
compatible = "synology,power-off";
reg = <0x12100 0x100>;
clocks = <&coreclk 0>;
};
ethernet@70000 {
pinctrl-names = "default";
phy = <&phy0>;
phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <0>;
status = "okay";
};
mdio@72004 {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
};
sata@a8000 {
pinctrl-names = "default";
pinctrl-0 = <&sata0_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
target-supply = <&reg_5v_sata0>;
};
};
bm@c8000 {
status = "okay";
};
usb3@f0000 {
usb-phy = <&usb3_0_phy>;
status = "okay";
};
usb3@f8000 {
usb-phy = <&usb3_1_phy>;
status = "okay";
};
};
bm-bppi {
status = "okay";
};
gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
<&gpio1 17 GPIO_ACTIVE_HIGH>,
<&gpio1 16 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
1500 1
2500 2
3000 3
3400 4
3700 5
3900 6
4000 7>;
cooling-cells = <2>;
};
gpio-leds {
compatible = "gpio-leds";
/* The green part is on gpio0.20 which is also used by
* sata0, and accesses to SATA disk 0 make it blink so it
* doesn't need to be declared here.
*/
orange {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
label = "ds116:orange:disk";
default-state = "off";
};
};
};
usb3_0_phy: usb3_0_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_usb3_0_vbus>;
};
usb3_1_phy: usb3_1_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_usb3_1_vbus>;
};
reg_usb3_0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus0";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};
reg_usb3_1_vbus: usb3-vbus1 {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus1";
pinctrl-names = "default";
pinctrl-0 = <&xhci1_vbus_pins>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
reg_sata0: pwr-sata0 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
regulator-boot-on;
gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata0: v5-sata0 {
compatible = "regulator-fixed";
regulator-name = "v5.0-sata0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_sata0>;
};
reg_12v_sata0: v12-sata0 {
compatible = "regulator-fixed";
regulator-name = "v12.0-sata0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&reg_sata0>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "macronix,mx25l6405d", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
/* Note: there is a redboot partition table despite u-boot
* being used. The names presented here are the same as those
* found in the FIS directory. There is also a small device
* tree in the last 64kB of the RedBoot partition which is not
* enumerated. The MAC address and the serial number are listed
* in the "vendor" partition.
*/
partition@00000000 {
label = "RedBoot";
reg = <0x00000000 0x000f0000>;
read-only;
};
partition@000c0000 {
label = "zImage";
reg = <0x000f0000 0x002d0000>;
};
partition@00390000 {
label = "rd.gz";
reg = <0x003c0000 0x00410000>;
};
partition@007d0000 {
label = "vendor";
reg = <0x007d0000 0x00010000>;
read-only;
};
partition@007e0000 {
label = "RedBoot config";
reg = <0x007e0000 0x00010000>;
read-only;
};
partition@007f0000 {
label = "FIS directory";
reg = <0x007f0000 0x00010000>;
read-only;
};
};
};
&pinctrl {
/* use only one pin for UART1, as mpp20 is used by sata0 */
uart1_pins: uart-pins-1 {
marvell,pins = "mpp19";
marvell,function = "ua1";
};
xhci0_vbus_pins: xhci0_vbus_pins {
marvell,pins = "mpp58";
marvell,function = "gpio";
};
xhci1_vbus_pins: xhci1_vbus_pins {
marvell,pins = "mpp59";
marvell,function = "gpio";
};
};
...@@ -70,13 +70,7 @@ cpu@1 { ...@@ -70,13 +70,7 @@ cpu@1 {
}; };
soc { soc {
internal-regs { pciec: pcie-controller {
pinctrl@18000 {
compatible = "marvell,mv88f6820-pinctrl";
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie"; compatible = "marvell,armada-370-pcie";
status = "disabled"; status = "disabled";
device_type = "pci"; device_type = "pci";
...@@ -106,7 +100,7 @@ pcie-controller { ...@@ -106,7 +100,7 @@ pcie-controller {
* configured in x4 by the bootloader, then * configured in x4 by the bootloader, then
* pcie@4,0 is not available. * pcie@4,0 is not available.
*/ */
pcie@1,0 { pcie1: pcie@1,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>; reg = <0x0800 0 0 0 0>;
...@@ -124,7 +118,7 @@ pcie@1,0 { ...@@ -124,7 +118,7 @@ pcie@1,0 {
}; };
/* x1 port */ /* x1 port */
pcie@2,0 { pcie2: pcie@2,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>; reg = <0x1000 0 0 0 0>;
...@@ -142,7 +136,7 @@ pcie@2,0 { ...@@ -142,7 +136,7 @@ pcie@2,0 {
}; };
/* x1 port */ /* x1 port */
pcie@3,0 { pcie3: pcie@3,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>; reg = <0x1800 0 0 0 0>;
...@@ -163,7 +157,7 @@ pcie@3,0 { ...@@ -163,7 +157,7 @@ pcie@3,0 {
* x1 port only available when pcie@1,0 is * x1 port only available when pcie@1,0 is
* configured as a x1 port * configured as a x1 port
*/ */
pcie@4,0 { pcie4: pcie@4,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>; reg = <0x2000 0 0 0 0>;
...@@ -182,3 +176,7 @@ pcie@4,0 { ...@@ -182,3 +176,7 @@ pcie@4,0 {
}; };
}; };
}; };
&pinctrl {
compatible = "marvell,mv88f6820-pinctrl";
};
...@@ -50,13 +50,8 @@ / { ...@@ -50,13 +50,8 @@ / {
model = "Marvell Armada 388 family SoC"; model = "Marvell Armada 388 family SoC";
compatible = "marvell,armada388", "marvell,armada385", compatible = "marvell,armada388", "marvell,armada385",
"marvell,armada380"; "marvell,armada380";
soc { soc {
internal-regs { internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6828-pinctrl";
};
sata@e0000 { sata@e0000 {
compatible = "marvell,armada-380-ahci"; compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>; reg = <0xe0000 0x2000>;
...@@ -68,3 +63,7 @@ sata@e0000 { ...@@ -68,3 +63,7 @@ sata@e0000 {
}; };
}; };
}; };
&pinctrl {
compatible = "marvell,mv88f6828-pinctrl";
};
...@@ -82,7 +82,7 @@ bootrom { ...@@ -82,7 +82,7 @@ bootrom {
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
}; };
devbus-bootcs { devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
...@@ -92,7 +92,7 @@ devbus-bootcs { ...@@ -92,7 +92,7 @@ devbus-bootcs {
status = "disabled"; status = "disabled";
}; };
devbus-cs0 { devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
...@@ -102,7 +102,7 @@ devbus-cs0 { ...@@ -102,7 +102,7 @@ devbus-cs0 {
status = "disabled"; status = "disabled";
}; };
devbus-cs1 { devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
...@@ -112,7 +112,7 @@ devbus-cs1 { ...@@ -112,7 +112,7 @@ devbus-cs1 {
status = "disabled"; status = "disabled";
}; };
devbus-cs2 { devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
...@@ -122,7 +122,7 @@ devbus-cs2 { ...@@ -122,7 +122,7 @@ devbus-cs2 {
status = "disabled"; status = "disabled";
}; };
devbus-cs3 { devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
...@@ -339,7 +339,7 @@ gpio1: gpio@18140 { ...@@ -339,7 +339,7 @@ gpio1: gpio@18140 {
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
}; };
system-controller@18200 { systemc: system-controller@18200 {
compatible = "marvell,armada-380-system-controller", compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller"; "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>; reg = <0x18200 0x100>;
...@@ -360,7 +360,8 @@ coreclk: mvebu-sar@18600 { ...@@ -360,7 +360,8 @@ coreclk: mvebu-sar@18600 {
mbusc: mbus-controller@20000 { mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller"; compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>; reg = <0x20000 0x100>, <0x20180 0x20>,
<0x20250 0x8>;
}; };
mpic: interrupt-controller@20a00 { mpic: interrupt-controller@20a00 {
...@@ -373,7 +374,7 @@ mpic: interrupt-controller@20a00 { ...@@ -373,7 +374,7 @@ mpic: interrupt-controller@20a00 {
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
}; };
timer@20300 { timer: timer@20300 {
compatible = "marvell,armada-380-timer", compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer"; "marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>; reg = <0x20300 0x30>, <0x21040 0x30>;
...@@ -387,14 +388,14 @@ timer@20300 { ...@@ -387,14 +388,14 @@ timer@20300 {
clock-names = "nbclk", "fixed"; clock-names = "nbclk", "fixed";
}; };
watchdog@20300 { watchdog: watchdog@20300 {
compatible = "marvell,armada-380-wdt"; compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>; clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed"; clock-names = "nbclk", "fixed";
}; };
cpurst@20800 { cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset"; compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>; reg = <0x20800 0x10>;
}; };
...@@ -404,12 +405,12 @@ mpcore-soc-ctrl@20d20 { ...@@ -404,12 +405,12 @@ mpcore-soc-ctrl@20d20 {
reg = <0x20d20 0x6c>; reg = <0x20d20 0x6c>;
}; };
coherency-fabric@21010 { coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric"; compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>; reg = <0x21010 0x1c>;
}; };
pmsu@22000 { pmsu: pmsu@22000 {
compatible = "marvell,armada-380-pmsu"; compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>; reg = <0x22000 0x1000>;
}; };
...@@ -451,7 +452,7 @@ eth2: ethernet@34000 { ...@@ -451,7 +452,7 @@ eth2: ethernet@34000 {
status = "disabled"; status = "disabled";
}; };
usb@58000 { usb0: usb@58000 {
compatible = "marvell,orion-ehci"; compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>; reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
...@@ -459,7 +460,7 @@ usb@58000 { ...@@ -459,7 +460,7 @@ usb@58000 {
status = "disabled"; status = "disabled";
}; };
xor@60800 { xor0: xor@60800 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor"; compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100 reg = <0x60800 0x100
0x60a00 0x100>; 0x60a00 0x100>;
...@@ -479,7 +480,7 @@ xor01 { ...@@ -479,7 +480,7 @@ xor01 {
}; };
}; };
xor@60900 { xor1: xor@60900 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor"; compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100 reg = <0x60900 0x100
0x60b00 0x100>; 0x60b00 0x100>;
...@@ -507,7 +508,7 @@ mdio: mdio@72004 { ...@@ -507,7 +508,7 @@ mdio: mdio@72004 {
clocks = <&gateclk 4>; clocks = <&gateclk 4>;
}; };
crypto@90000 { cesa: crypto@90000 {
compatible = "marvell,armada-38x-crypto"; compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>; reg = <0x90000 0x10000>;
reg-names = "regs"; reg-names = "regs";
...@@ -522,7 +523,7 @@ crypto@90000 { ...@@ -522,7 +523,7 @@ crypto@90000 {
marvell,crypto-sram-size = <0x800>; marvell,crypto-sram-size = <0x800>;
}; };
rtc@a3800 { rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc"; compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>; reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc"; reg-names = "rtc", "rtc-soc";
...@@ -561,13 +562,13 @@ coredivclk: clock@e4250 { ...@@ -561,13 +562,13 @@ coredivclk: clock@e4250 {
clock-output-names = "nand"; clock-output-names = "nand";
}; };
thermal@e8078 { thermal: thermal@e8078 {
compatible = "marvell,armada380-thermal"; compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4074 0x4>; reg = <0xe4078 0x4>, <0xe4074 0x4>;
status = "okay"; status = "okay";
}; };
flash@d0000 { nand: flash@d0000 {
compatible = "marvell,armada370-nand"; compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>; reg = <0xd0000 0x54>;
#address-cells = <1>; #address-cells = <1>;
...@@ -577,7 +578,7 @@ flash@d0000 { ...@@ -577,7 +578,7 @@ flash@d0000 {
status = "disabled"; status = "disabled";
}; };
sdhci@d8000 { sdhci: sdhci@d8000 {
compatible = "marvell,armada-380-sdhci"; compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3"; reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>, reg = <0xd8000 0x1000>,
......
...@@ -45,11 +45,14 @@ ...@@ -45,11 +45,14 @@
* common to all Armada XP SoCs. * common to all Armada XP SoCs.
*/ */
#include "armada-xp.dtsi" #include "armada-370-xp.dtsi"
/ { / {
#address-cells = <2>;
#size-cells = <2>;
model = "Marvell 98DX3236 SoC"; model = "Marvell 98DX3236 SoC";
compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
aliases { aliases {
gpio0 = &gpio0; gpio0 = &gpio0;
...@@ -72,12 +75,19 @@ cpu@0 { ...@@ -72,12 +75,19 @@ cpu@0 {
}; };
soc { soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>; MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
/* /*
* 98DX3236 has 1 x1 PCIe unit Gen2.0 * 98DX3236 has 1 x1 PCIe unit Gen2.0
*/ */
...@@ -95,8 +105,7 @@ pciec: pcie-controller@82000000 { ...@@ -95,8 +105,7 @@ pciec: pcie-controller@82000000 {
ranges = ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
pcie1: pcie@1,0 { pcie1: pcie@1,0 {
device_type = "pci"; device_type = "pci";
...@@ -117,31 +126,86 @@ pcie1: pcie@1,0 { ...@@ -117,31 +126,86 @@ pcie1: pcie@1,0 {
}; };
internal-regs { internal-regs {
coreclk: mvebu-sar@18230 { sdramc@1400 {
compatible = "marvell,mv98dx3236-core-clock"; compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
cache-level = <2>;
cache-unified;
wt-override;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
/* does not exist */
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
status = "disabled";
};
gpio2: gpio@18180 { /* rework some properties */
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <1>; /* only gpio #32 */
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>;
};
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,mv98dx3236-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
}; };
cpuclk: clock-complex@18700 { cpuclk: clock-complex@18700 {
#clock-cells = <1>;
compatible = "marvell,mv98dx3236-cpu-clock"; compatible = "marvell,mv98dx3236-cpu-clock";
reg = <0x18700 0x24>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
}; };
corediv-clock@18740 { corediv-clock@18740 {
status = "disabled"; status = "disabled";
}; };
xor@60900 { cpu-config@21000 {
status = "disabled"; compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
}; };
crypto@90000 { ethernet@70000 {
status = "disabled"; compatible = "marvell,armada-xp-neta";
}; };
xor@f0900 { ethernet@74000 {
status = "disabled"; compatible = "marvell,armada-xp-neta";
}; };
xor@f0800 { xor1: xor@f0800 {
compatible = "marvell,orion-xor"; compatible = "marvell,orion-xor";
reg = <0xf0800 0x100 reg = <0xf0800 0x100
0xf0a00 0x100>; 0xf0a00 0x100>;
...@@ -161,45 +225,43 @@ xor11 { ...@@ -161,45 +225,43 @@ xor11 {
}; };
}; };
gpio0: gpio@18100 { nand: nand@d0000 {
compatible = "marvell,orion-gpio"; clocks = <&dfx_coredivclk 0>;
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
/* does not exist */
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
status = "disabled";
}; };
gpio2: gpio@18180 { /* rework some properties */ xor0: xor@f0900 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-xor";
reg = <0x18180 0x40>; reg = <0xF0900 0x100
ngpios = <1>; /* only gpio #32 */ 0xF0B00 0x100>;
gpio-controller; clocks = <&gateclk 28>;
#gpio-cells = <2>; status = "okay";
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>;
};
nand: nand@d0000 { xor00 {
clocks = <&dfx_coredivclk 0>; interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
}; };
}; };
dfxr: dfx-registers@ac000000 { dfx: dfx-server@ac000000 {
compatible = "simple-bus"; compatible = "marvell,dfx-server", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
coreclk: mvebu-sar@f8204 {
compatible = "marvell,mv98dx3236-core-clock";
reg = <0xf8204 0x4>;
#clock-cells = <1>;
};
dfx_coredivclk: corediv-clock@f8268 { dfx_coredivclk: corediv-clock@f8268 {
compatible = "marvell,mv98dx3236-corediv-clock"; compatible = "marvell,mv98dx3236-corediv-clock";
...@@ -208,11 +270,6 @@ dfx_coredivclk: corediv-clock@f8268 { ...@@ -208,11 +270,6 @@ dfx_coredivclk: corediv-clock@f8268 {
clocks = <&mainpll>; clocks = <&mainpll>;
clock-output-names = "nand"; clock-output-names = "nand";
}; };
dfx: dfx@0 {
compatible = "marvell,dfx-server";
reg = <0 0x100000>;
};
}; };
switch: switch@a8000000 { switch: switch@a8000000 {
...@@ -229,6 +286,53 @@ pp0: packet-processor@0 { ...@@ -229,6 +286,53 @@ pp0: packet-processor@0 {
}; };
}; };
}; };
clocks {
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&watchdog {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&cpurst {
reg = <0x20800 0x20>;
};
&usb0 {
clocks = <&gateclk 18>;
};
&usb1 {
clocks = <&gateclk 19>;
}; };
&pinctrl { &pinctrl {
...@@ -241,14 +345,13 @@ spi0_pins: spi0-pins { ...@@ -241,14 +345,13 @@ spi0_pins: spi0-pins {
}; };
}; };
&sdio { &spi0 {
status = "disabled"; compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
}; };
&crypto_sram0 { &sdio {
status = "disabled"; status = "disabled";
}; };
&crypto_sram1 {
status = "disabled";
};
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
/ { / {
model = "Marvell 98DX3336 SoC"; model = "Marvell 98DX3336 SoC";
compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
cpus { cpus {
cpu@1 { cpu@1 {
......
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
/ { / {
model = "Marvell 98DX4251 SoC"; model = "Marvell 98DX4251 SoC";
compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
cpus { cpus {
cpu@1 { cpu@1 {
......
...@@ -58,7 +58,7 @@ ...@@ -58,7 +58,7 @@
/ { / {
model = "Marvell Bobcat2 Evaluation Board"; model = "Marvell Bobcat2 Evaluation Board";
compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
chosen { chosen {
bootargs = "console=ttyS0,115200 earlyprintk"; bootargs = "console=ttyS0,115200 earlyprintk";
......
...@@ -58,7 +58,7 @@ ...@@ -58,7 +58,7 @@
/ { / {
model = "DB-XC3-24G4XG"; model = "DB-XC3-24G4XG";
compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
chosen { chosen {
bootargs = "console=ttyS0,115200 earlyprintk"; bootargs = "console=ttyS0,115200 earlyprintk";
......
...@@ -71,7 +71,8 @@ soc { ...@@ -71,7 +71,8 @@ soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
internal-regs { internal-regs {
...@@ -95,6 +96,9 @@ ethernet@70000 { ...@@ -95,6 +96,9 @@ ethernet@70000 {
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
fixed-link { fixed-link {
speed = <1000>; speed = <1000>;
full-duplex; full-duplex;
...@@ -106,6 +110,9 @@ ethernet@74000 { ...@@ -106,6 +110,9 @@ ethernet@74000 {
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
fixed-link { fixed-link {
speed = <1000>; speed = <1000>;
full-duplex; full-duplex;
...@@ -156,6 +163,7 @@ wlan_5g@3 { ...@@ -156,6 +163,7 @@ wlan_5g@3 {
esata@4 { esata@4 {
label = "mamba:white:esata"; label = "mamba:white:esata";
reg = <0x4>; reg = <0x4>;
linux,default-trigger = "disk-activity";
}; };
usb2@5 { usb2@5 {
...@@ -185,6 +193,10 @@ wps_amber@9 { ...@@ -185,6 +193,10 @@ wps_amber@9 {
}; };
}; };
bm@c8000 {
status = "okay";
};
nand@d0000 { nand@d0000 {
status = "okay"; status = "okay";
num-cs = <1>; num-cs = <1>;
...@@ -258,6 +270,10 @@ partition@180000 { ...@@ -258,6 +270,10 @@ partition@180000 {
}; };
}; };
}; };
bm-bppi {
status = "okay";
};
}; };
gpio_keys { gpio_keys {
......
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