Commit b99bffd1 authored by Jim Bride's avatar Jim Bride Committed by Greg Kroah-Hartman

drm/i915/hsw: Fix workaround for server AUX channel clock divisor

commit e058c945 upstream.

According to the HSW b-spec we need to try clock divisors of 63
and 72, each 3 or more times, when attempting DP AUX channel
communication on a server chipset.  This actually wasn't happening
due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit
in status rather than checking that the operation was done and
that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

[v2] Implemented alternate solution suggested by Jani Nikula.
Signed-off-by: default avatarJim Bride <jim.bride@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f5ea938c
......@@ -481,10 +481,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_RECEIVE_ERROR))
continue;
if (status & DP_AUX_CH_CTL_DONE)
break;
goto done;
}
if (status & DP_AUX_CH_CTL_DONE)
break;
}
if ((status & DP_AUX_CH_CTL_DONE) == 0) {
......@@ -493,6 +491,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
goto out;
}
done:
/* Check for timeout or receive error.
* Timeouts occur when the sink is not connected
*/
......
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