Commit bc6fe533 authored by Dave Airlie's avatar Dave Airlie

Merge tag 'drm-intel-fixes-2018-01-04' of...

Merge tag 'drm-intel-fixes-2018-01-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

drm/i915 fixes for v4.15-rc7
- couple of documentation build fixes
- serialize non-blocking modesets
- prevent DMC from messing up GMBUS transfers
- PSR regression fix

* tag 'drm-intel-fixes-2018-01-04' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
  docs: fix, intel_guc_loader.c has been moved to intel_guc_fw.c
  documentation/gpu/i915: fix docs build error after file rename
  drm/i915: Put all non-blocking modesets onto an ordered wq
  drm/i915: Disable DC states around GMBUS on GLK
  drm/i915/psr: Fix register name mess up.
parents 0007b9ca 30414f30
...@@ -341,10 +341,7 @@ GuC ...@@ -341,10 +341,7 @@ GuC
GuC-specific firmware loader GuC-specific firmware loader
---------------------------- ----------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
:doc: GuC-specific firmware loader
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
:internal: :internal:
GuC-based command submission GuC-based command submission
......
...@@ -2368,6 +2368,9 @@ struct drm_i915_private { ...@@ -2368,6 +2368,9 @@ struct drm_i915_private {
*/ */
struct workqueue_struct *wq; struct workqueue_struct *wq;
/* ordered wq for modesets */
struct workqueue_struct *modeset_wq;
/* Display functions */ /* Display functions */
struct drm_i915_display_funcs display; struct drm_i915_display_funcs display;
......
...@@ -6977,6 +6977,7 @@ enum { ...@@ -6977,6 +6977,7 @@ enum {
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4) #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
#define MASK_WAKEMEM (1<<13) #define MASK_WAKEMEM (1<<13)
#define SKL_DFSM _MMIO(0x51000) #define SKL_DFSM _MMIO(0x51000)
...@@ -8522,6 +8523,7 @@ enum skl_power_gate { ...@@ -8522,6 +8523,7 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff) #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
......
...@@ -860,16 +860,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, ...@@ -860,16 +860,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
{ {
int min_cdclk = skl_calc_cdclk(0, vco);
u32 val; u32 val;
WARN_ON(vco != 8100000 && vco != 8640000); WARN_ON(vco != 8100000 && vco != 8640000);
/* select the minimum CDCLK before enabling DPLL 0 */
val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
I915_WRITE(CDCLK_CTL, val);
POSTING_READ(CDCLK_CTL);
/* /*
* We always enable DPLL0 with the lowest link rate possible, but still * We always enable DPLL0 with the lowest link rate possible, but still
* taking into account the VCO required to operate the eDP panel at the * taking into account the VCO required to operate the eDP panel at the
...@@ -923,7 +917,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -923,7 +917,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
{ {
int cdclk = cdclk_state->cdclk; int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco; int vco = cdclk_state->vco;
u32 freq_select, pcu_ack; u32 freq_select, pcu_ack, cdclk_ctl;
int ret; int ret;
WARN_ON((cdclk == 24000) != (vco == 0)); WARN_ON((cdclk == 24000) != (vco == 0));
...@@ -940,7 +934,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -940,7 +934,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
return; return;
} }
/* set CDCLK_CTL */ /* Choose frequency for this cdclk */
switch (cdclk) { switch (cdclk) {
case 450000: case 450000:
case 432000: case 432000:
...@@ -968,10 +962,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -968,10 +962,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
dev_priv->cdclk.hw.vco != vco) dev_priv->cdclk.hw.vco != vco)
skl_dpll0_disable(dev_priv); skl_dpll0_disable(dev_priv);
cdclk_ctl = I915_READ(CDCLK_CTL);
if (dev_priv->cdclk.hw.vco != vco) {
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
I915_WRITE(CDCLK_CTL, cdclk_ctl);
}
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
I915_WRITE(CDCLK_CTL, cdclk_ctl);
POSTING_READ(CDCLK_CTL);
if (dev_priv->cdclk.hw.vco != vco) if (dev_priv->cdclk.hw.vco != vco)
skl_dpll0_enable(dev_priv, vco); skl_dpll0_enable(dev_priv, vco);
I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); /* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
I915_WRITE(CDCLK_CTL, cdclk_ctl);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
I915_WRITE(CDCLK_CTL, cdclk_ctl);
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
I915_WRITE(CDCLK_CTL, cdclk_ctl);
POSTING_READ(CDCLK_CTL); POSTING_READ(CDCLK_CTL);
/* inform PCU of the change */ /* inform PCU of the change */
......
...@@ -12544,11 +12544,15 @@ static int intel_atomic_commit(struct drm_device *dev, ...@@ -12544,11 +12544,15 @@ static int intel_atomic_commit(struct drm_device *dev,
INIT_WORK(&state->commit_work, intel_atomic_commit_work); INIT_WORK(&state->commit_work, intel_atomic_commit_work);
i915_sw_fence_commit(&intel_state->commit_ready); i915_sw_fence_commit(&intel_state->commit_ready);
if (nonblock) if (nonblock && intel_state->modeset) {
queue_work(dev_priv->modeset_wq, &state->commit_work);
} else if (nonblock) {
queue_work(system_unbound_wq, &state->commit_work); queue_work(system_unbound_wq, &state->commit_work);
else } else {
if (intel_state->modeset)
flush_workqueue(dev_priv->modeset_wq);
intel_atomic_commit_tail(state); intel_atomic_commit_tail(state);
}
return 0; return 0;
} }
...@@ -14462,6 +14466,8 @@ int intel_modeset_init(struct drm_device *dev) ...@@ -14462,6 +14466,8 @@ int intel_modeset_init(struct drm_device *dev)
enum pipe pipe; enum pipe pipe;
struct intel_crtc *crtc; struct intel_crtc *crtc;
dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
drm_mode_config_init(dev); drm_mode_config_init(dev);
dev->mode_config.min_width = 0; dev->mode_config.min_width = 0;
...@@ -15270,6 +15276,8 @@ void intel_modeset_cleanup(struct drm_device *dev) ...@@ -15270,6 +15276,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_cleanup_gt_powersave(dev_priv); intel_cleanup_gt_powersave(dev_priv);
intel_teardown_gmbus(dev_priv); intel_teardown_gmbus(dev_priv);
destroy_workqueue(dev_priv->modeset_wq);
} }
void intel_connector_attach_encoder(struct intel_connector *connector, void intel_connector_attach_encoder(struct intel_connector *connector,
......
...@@ -590,7 +590,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, ...@@ -590,7 +590,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
if (dev_priv->psr.active) { if (dev_priv->psr.active) {
i915_reg_t psr_ctl; i915_reg_t psr_status;
u32 psr_status_mask; u32 psr_status_mask;
if (dev_priv->psr.aux_frame_sync) if (dev_priv->psr.aux_frame_sync)
...@@ -599,24 +599,24 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, ...@@ -599,24 +599,24 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
0); 0);
if (dev_priv->psr.psr2_support) { if (dev_priv->psr.psr2_support) {
psr_ctl = EDP_PSR2_CTL; psr_status = EDP_PSR2_STATUS_CTL;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
I915_WRITE(psr_ctl, I915_WRITE(EDP_PSR2_CTL,
I915_READ(psr_ctl) & I915_READ(EDP_PSR2_CTL) &
~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
} else { } else {
psr_ctl = EDP_PSR_STATUS_CTL; psr_status = EDP_PSR_STATUS_CTL;
psr_status_mask = EDP_PSR_STATUS_STATE_MASK; psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
I915_WRITE(psr_ctl, I915_WRITE(EDP_PSR_CTL,
I915_READ(psr_ctl) & ~EDP_PSR_ENABLE); I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
} }
/* Wait till PSR is idle */ /* Wait till PSR is idle */
if (intel_wait_for_register(dev_priv, if (intel_wait_for_register(dev_priv,
psr_ctl, psr_status_mask, 0, psr_status, psr_status_mask, 0,
2000)) 2000))
DRM_ERROR("Timed out waiting for PSR Idle State\n"); DRM_ERROR("Timed out waiting for PSR Idle State\n");
......
...@@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) ...@@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling DC5\n"); DRM_DEBUG_KMS("Enabling DC5\n");
/* Wa Display #1183: skl,kbl,cfl */
if (IS_GEN9_BC(dev_priv))
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
SKL_SELECT_ALTERNATE_DC_EXIT);
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
} }
...@@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv) ...@@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
{ {
DRM_DEBUG_KMS("Disabling DC6\n"); DRM_DEBUG_KMS("Disabling DC6\n");
/* Wa Display #1183: skl,kbl,cfl */
if (IS_GEN9_BC(dev_priv))
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
SKL_SELECT_ALTERNATE_DC_EXIT);
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
} }
...@@ -1786,6 +1796,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, ...@@ -1786,6 +1796,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_GMBUS) | \
BIT_ULL(POWER_DOMAIN_INIT)) BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
......
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