ARM: dts: exynos: Fix watchdog reset on Exynos4412

The Exynos4412 has the same watchdog as newer SoCs (e.g. Exynos5250).
Just like the others, for working it requires additional steps in Power
Management Unit: unmasking the reset request and enabling the system
reset.  Without these additional steps in PMU, the watchdog will not be
able to reset the system on expiration event.

Change the compatible of Exynos4412 watchdog device node to
samsung,exynos5250-wdt which includes the additional PMU steps.

This will also fix infinite watchdog interrupt in soft mode (lack of
interrupt clear) because it is also included in samsung,exynos5250-wdt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>

arch/arm/boot/dts/exynos4.dtsi

@@ -283,15 +283,6 @@ csis_1: csis@11890000 {
 		};
 	};
 
-	watchdog: watchdog@10060000 {
-		compatible = "samsung,s3c2410-wdt";
-		reg = <0x10060000 0x100>;
-		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clock CLK_WDT>;
-		clock-names = "watchdog";
-		status = "disabled";
-	};
-
 	rtc: rtc@10070000 {
 		compatible = "samsung,s3c6410-rtc";
 		reg = <0x10070000 0x100>;

arch/arm/boot/dts/exynos4210.dtsi

@@ -119,6 +119,15 @@ mct_map: mct-map {
 		};
 	};
 
+	watchdog: watchdog@10060000 {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x10060000 0x100>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clock CLK_WDT>;
+		clock-names = "watchdog";
+		status = "disabled";
+	};
+
 	clock: clock-controller@10030000 {
 		compatible = "samsung,exynos4210-clock";
 		reg = <0x10030000 0x20000>;

arch/arm/boot/dts/exynos4412.dtsi

@@ -215,6 +215,16 @@ mct_map: mct-map {
 		};
 	};
 
+	watchdog: watchdog@10060000 {
+		compatible = "samsung,exynos5250-wdt";
+		reg = <0x10060000 0x100>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clock CLK_WDT>;
+		clock-names = "watchdog";
+		samsung,syscon-phandle = <&pmu_system_controller>;
+		status = "disabled";
+	};
+
 	adc: adc@126C0000 {
 		compatible = "samsung,exynos-adc-v1";
 		reg = <0x126C0000 0x100>;