Commit c4d7e58f authored by Paul Walmsley's avatar Paul Walmsley

OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_"

Now that OMAP4-specific PRCM functions have been added, distinguish the
existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_".

This patch should not result in any functional change.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarRajendra Nayak <rnayak@ti.com>
parent dac9a771
...@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) ...@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
apll_mask = EN_APLL_LOCKED << clk->enable_bit; apll_mask = EN_APLL_LOCKED << clk->enable_bit;
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
if ((cval & apll_mask) == apll_mask) if ((cval & apll_mask) == apll_mask)
return 0; /* apll already enabled */ return 0; /* apll already enabled */
cval &= ~apll_mask; cval &= ~apll_mask;
cval |= apll_mask; cval |= apll_mask;
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_wait_idlest(cm_idlest_pll, status_mask, omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
OMAP24XX_CM_IDLEST_VAL, clk->name); OMAP24XX_CM_IDLEST_VAL, clk->name);
...@@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk) ...@@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk)
{ {
u32 cval; u32 cval;
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
cval &= ~(EN_APLL_LOCKED << clk->enable_bit); cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
} }
/* Public data */ /* Public data */
...@@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void) ...@@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void)
{ {
u32 aplls, srate = 0; u32 aplls, srate = 0;
aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls &= OMAP24XX_APLLS_CLKIN_MASK;
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
......
...@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) ...@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
core_clk = omap2_get_dpll_rate(clk); core_clk = omap2_get_dpll_rate(clk);
v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
v &= OMAP24XX_CORE_CLK_SRC_MASK; v &= OMAP24XX_CORE_CLK_SRC_MASK;
if (v == CORE_CLK_SRC_32K) if (v == CORE_CLK_SRC_32K)
...@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) ...@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
{ {
u32 high, low, core_clk_src; u32 high, low, core_clk_src;
core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
...@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) ...@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
const struct dpll_data *dd; const struct dpll_data *dd;
cur_rate = omap2xxx_clk_get_core_rate(dclk); cur_rate = omap2xxx_clk_get_core_rate(dclk);
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
mult &= OMAP24XX_CORE_CLK_SRC_MASK; mult &= OMAP24XX_CORE_CLK_SRC_MASK;
if ((rate == (cur_rate / 2)) && (mult == 2)) { if ((rate == (cur_rate / 2)) && (mult == 2)) {
...@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) ...@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
tmpset.cm_clksel1_pll &= ~(dd->mult_mask | tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
dd->div1_mask); dd->div1_mask);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1); div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
if (rate > low) { if (rate > low) {
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
......
...@@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) ...@@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
done_rate = CORE_CLK_SRC_DPLL; done_rate = CORE_CLK_SRC_DPLL;
/* MPU divider */ /* MPU divider */
cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
/* dsp + iva1 div(2420), iva2.1(2430) */ /* dsp + iva1 div(2420), iva2.1(2430) */
cm_write_mod_reg(prcm->cm_clksel_dsp, omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
OMAP24XX_DSP_MOD, CM_CLKSEL); OMAP24XX_DSP_MOD, CM_CLKSEL);
cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
/* Major subsystem dividers */ /* Major subsystem dividers */
tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
CM_CLKSEL1); CM_CLKSEL1);
if (cpu_is_omap2430()) if (cpu_is_omap2430())
cm_write_mod_reg(prcm->cm_clksel_mdm, omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
OMAP2430_MDM_MOD, CM_CLKSEL); OMAP2430_MDM_MOD, CM_CLKSEL);
/* x2 to enter omap2xxx_sdrc_init_params() */ /* x2 to enter omap2xxx_sdrc_init_params() */
......
...@@ -13,7 +13,6 @@ ...@@ -13,7 +13,6 @@
*/ */
#undef DEBUG #undef DEBUG
#include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/list.h> #include <linux/list.h>
...@@ -30,7 +29,6 @@ ...@@ -30,7 +29,6 @@
#include "prm2xxx_3xxx.h" #include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h" #include "prm-regbits-24xx.h"
#include "cm2xxx_3xxx.h" #include "cm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/powerdomain.h> #include <plat/powerdomain.h>
...@@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ...@@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
pr_debug("clockdomain: hardware will wake up %s when %s wakes " pr_debug("clockdomain: hardware will wake up %s when %s wakes "
"up\n", clkdm1->name, clkdm2->name); "up\n", clkdm1->name, clkdm2->name);
prm_set_mod_reg_bits((1 << clkdm2->dep_bit), omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
} }
...@@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ...@@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
pr_debug("clockdomain: hardware will no longer wake up %s " pr_debug("clockdomain: hardware will no longer wake up %s "
"after %s wakes up\n", clkdm1->name, clkdm2->name); "after %s wakes up\n", clkdm1->name, clkdm2->name);
prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
} }
...@@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ...@@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
} }
/* XXX It's faster to return the atomic wkdep_usecount */ /* XXX It's faster to return the atomic wkdep_usecount */
return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
(1 << clkdm2->dep_bit)); (1 << clkdm2->dep_bit));
} }
...@@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) ...@@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
atomic_set(&cd->wkdep_usecount, 0); atomic_set(&cd->wkdep_usecount, 0);
} }
prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
return 0; return 0;
} }
...@@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ...@@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
pr_debug("clockdomain: will prevent %s from sleeping if %s " pr_debug("clockdomain: will prevent %s from sleeping if %s "
"is active\n", clkdm1->name, clkdm2->name); "is active\n", clkdm1->name, clkdm2->name);
cm_set_mod_reg_bits((1 << clkdm2->dep_bit), omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP); OMAP3430_CM_SLEEPDEP);
} }
...@@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ...@@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
"sleeping if %s is active\n", clkdm1->name, "sleeping if %s is active\n", clkdm1->name,
clkdm2->name); clkdm2->name);
cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP); OMAP3430_CM_SLEEPDEP);
} }
...@@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ...@@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
} }
/* XXX It's faster to return the atomic sleepdep_usecount */ /* XXX It's faster to return the atomic sleepdep_usecount */
return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP, OMAP3430_CM_SLEEPDEP,
(1 << clkdm2->dep_bit)); (1 << clkdm2->dep_bit));
} }
...@@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) ...@@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
atomic_set(&cd->sleepdep_usecount, 0); atomic_set(&cd->sleepdep_usecount, 0);
} }
prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP); OMAP3430_CM_SLEEPDEP);
return 0; return 0;
...@@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) ...@@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
...@@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) ...@@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
if (cpu_is_omap24xx()) { if (cpu_is_omap24xx()) {
cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
......
This diff is collapsed.
...@@ -104,14 +104,14 @@ ...@@ -104,14 +104,14 @@
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
extern u32 cm_read_mod_reg(s16 module, u16 idx); extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
u8 idlest_shift); u8 idlest_shift);
extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
#endif #endif
......
...@@ -252,13 +252,13 @@ void omap3_clear_scratchpad_contents(void) ...@@ -252,13 +252,13 @@ void omap3_clear_scratchpad_contents(void)
void __iomem *v_addr; void __iomem *v_addr;
u32 offset = 0; u32 offset = 0;
v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
OMAP3430_GLOBAL_COLD_RST_MASK) { OMAP3430_GLOBAL_COLD_RST_MASK) {
for ( ; offset <= max_offset; offset += 0x4) for ( ; offset <= max_offset; offset += 0x4)
__raw_writel(0x0, (v_addr + offset)); __raw_writel(0x0, (v_addr + offset));
prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
OMAP3430_GR_MOD, OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET); OMAP3_PRM_RSTST_OFFSET);
} }
} }
...@@ -300,32 +300,34 @@ void omap3_save_scratchpad_contents(void) ...@@ -300,32 +300,34 @@ void omap3_save_scratchpad_contents(void)
scratchpad_contents.sdrc_block_offset = 0x64; scratchpad_contents.sdrc_block_offset = 0x64;
/* Populate the PRCM block contents */ /* Populate the PRCM block contents */
prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, prcm_block_contents.prm_clksrc_ctrl =
OMAP3_PRM_CLKSRC_CTRL_OFFSET); omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET);
OMAP3_PRM_CLKSEL_OFFSET); prcm_block_contents.prm_clksel =
omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
OMAP3_PRM_CLKSEL_OFFSET);
prcm_block_contents.cm_clksel_core = prcm_block_contents.cm_clksel_core =
cm_read_mod_reg(CORE_MOD, CM_CLKSEL); omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
prcm_block_contents.cm_clksel_wkup = prcm_block_contents.cm_clksel_wkup =
cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
prcm_block_contents.cm_clken_pll = prcm_block_contents.cm_clken_pll =
cm_read_mod_reg(PLL_MOD, CM_CLKEN); omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
prcm_block_contents.cm_autoidle_pll = prcm_block_contents.cm_autoidle_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll = prcm_block_contents.cm_clksel1_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll = prcm_block_contents.cm_clksel2_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.cm_clksel3_pll = prcm_block_contents.cm_clksel3_pll =
cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
prcm_block_contents.cm_clken_pll_mpu = prcm_block_contents.cm_clken_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
prcm_block_contents.cm_autoidle_pll_mpu = prcm_block_contents.cm_autoidle_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll_mpu = prcm_block_contents.cm_clksel1_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll_mpu = prcm_block_contents.cm_clksel2_pll_mpu =
cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.prcm_block_size = 0x0; prcm_block_contents.prcm_block_size = 0x0;
/* Populate the SDRC block contents */ /* Populate the SDRC block contents */
......
...@@ -38,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { ...@@ -38,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
.cpu_set_freq = omap_pm_cpu_set_freq, .cpu_set_freq = omap_pm_cpu_set_freq,
.cpu_get_freq = omap_pm_cpu_get_freq, .cpu_get_freq = omap_pm_cpu_get_freq,
#endif #endif
.dsp_prm_read = prm_read_mod_reg, .dsp_prm_read = omap2_prm_read_mod_reg,
.dsp_prm_write = prm_write_mod_reg, .dsp_prm_write = omap2_prm_write_mod_reg,
.dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits,
.dsp_cm_read = cm_read_mod_reg, .dsp_cm_read = omap2_cm_read_mod_reg,
.dsp_cm_write = cm_write_mod_reg, .dsp_cm_write = omap2_cm_write_mod_reg,
.dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
}; };
static int __init omap_dsp_init(void) static int __init omap_dsp_init(void)
......
...@@ -45,10 +45,10 @@ u32 wakeup_timer_milliseconds; ...@@ -45,10 +45,10 @@ u32 wakeup_timer_milliseconds;
#define DUMP_PRM_MOD_REG(mod, reg) \ #define DUMP_PRM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \ regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = prm_read_mod_reg(mod, reg) regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
#define DUMP_CM_MOD_REG(mod, reg) \ #define DUMP_CM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \ regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = cm_read_mod_reg(mod, reg) regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
#define DUMP_PRM_REG(reg) \ #define DUMP_PRM_REG(reg) \
regs[reg_count].name = #reg; \ regs[reg_count].name = #reg; \
regs[reg_count++].val = __raw_readl(reg) regs[reg_count++].val = __raw_readl(reg)
...@@ -328,10 +328,10 @@ static void pm_dbg_regset_store(u32 *ptr) ...@@ -328,10 +328,10 @@ static void pm_dbg_regset_store(u32 *ptr)
for (j = pm_dbg_reg_modules[i].low; for (j = pm_dbg_reg_modules[i].low;
j <= pm_dbg_reg_modules[i].high; j += 4) { j <= pm_dbg_reg_modules[i].high; j += 4) {
if (pm_dbg_reg_modules[i].type == MOD_CM) if (pm_dbg_reg_modules[i].type == MOD_CM)
val = cm_read_mod_reg( val = omap2_cm_read_mod_reg(
pm_dbg_reg_modules[i].offset, j); pm_dbg_reg_modules[i].offset, j);
else else
val = prm_read_mod_reg( val = omap2_prm_read_mod_reg(
pm_dbg_reg_modules[i].offset, j); pm_dbg_reg_modules[i].offset, j);
*(ptr++) = val; *(ptr++) = val;
} }
......
This diff is collapsed.
This diff is collapsed.
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
/* Common functions across OMAP2 and OMAP3 */ /* Common functions across OMAP2 and OMAP3 */
static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{ {
prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT), (pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
return 0; return 0;
...@@ -36,14 +36,16 @@ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) ...@@ -36,14 +36,16 @@ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); OMAP2_PM_PWSTCTRL,
OMAP_POWERSTATE_MASK);
} }
static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); OMAP2_PM_PWSTST,
OMAP_POWERSTATEST_MASK);
} }
static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
...@@ -53,8 +55,8 @@ static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, ...@@ -53,8 +55,8 @@ static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL); OMAP2_PM_PWSTCTRL);
return 0; return 0;
} }
...@@ -66,8 +68,8 @@ static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, ...@@ -66,8 +68,8 @@ static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
m = omap2_pwrdm_get_mem_bank_retst_mask(bank); m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL); OMAP2_PM_PWSTCTRL);
return 0; return 0;
} }
...@@ -78,7 +80,8 @@ static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) ...@@ -78,7 +80,8 @@ static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
m = omap2_pwrdm_get_mem_bank_stst_mask(bank); m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m); return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
m);
} }
static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
...@@ -87,7 +90,8 @@ static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) ...@@ -87,7 +90,8 @@ static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
m = omap2_pwrdm_get_mem_bank_retst_mask(bank); m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, m); return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL, m);
} }
static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
...@@ -95,8 +99,8 @@ static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) ...@@ -95,8 +99,8 @@ static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
u32 v; u32 v;
v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
return 0; return 0;
} }
...@@ -112,7 +116,7 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) ...@@ -112,7 +116,7 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
*/ */
/* XXX Is this udelay() value meaningful? */ /* XXX Is this udelay() value meaningful? */
while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
OMAP_INTRANSITION_MASK) && OMAP_INTRANSITION_MASK) &&
(c++ < PWRDM_TRANSITION_BAILOUT)) (c++ < PWRDM_TRANSITION_BAILOUT))
udelay(1); udelay(1);
...@@ -131,26 +135,30 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) ...@@ -131,26 +135,30 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
/* Applicable only for OMAP3. Not supported on OMAP2 */ /* Applicable only for OMAP3. Not supported on OMAP2 */
static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP3430_LASTPOWERSTATEENTERED_MASK); OMAP3430_PM_PREPWSTST,
OMAP3430_LASTPOWERSTATEENTERED_MASK);
} }
static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP3430_LOGICSTATEST_MASK); OMAP2_PM_PWSTST,
OMAP3430_LOGICSTATEST_MASK);
} }
static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP3430_LOGICSTATEST_MASK); OMAP2_PM_PWSTCTRL,
OMAP3430_LOGICSTATEST_MASK);
} }
static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP3430_LASTLOGICSTATEENTERED_MASK); OMAP3430_PM_PREPWSTST,
OMAP3430_LASTLOGICSTATEENTERED_MASK);
} }
static int omap3_get_mem_bank_lastmemst_mask(u8 bank) static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
...@@ -177,26 +185,28 @@ static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) ...@@ -177,26 +185,28 @@ static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
m = omap3_get_mem_bank_lastmemst_mask(bank); m = omap3_get_mem_bank_lastmemst_mask(bank);
return prm_read_mod_bits_shift(pwrdm->prcm_offs, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP3430_PM_PREPWSTST, m); OMAP3430_PM_PREPWSTST, m);
} }
static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{ {
prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
return 0; return 0;
} }
static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
{ {
return prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, return omap2_prm_rmw_mod_reg_bits(0,
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
} }
static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
{ {
return prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 0, pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL);
} }
struct pwrdm_ops omap2_pwrdm_operations = { struct pwrdm_ops omap2_pwrdm_operations = {
......
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{ {
prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT), (pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
return 0; return 0;
...@@ -33,25 +33,25 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) ...@@ -33,25 +33,25 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK);
} }
static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK); OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK);
} }
static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
OMAP4430_LASTPOWERSTATEENTERED_MASK); OMAP4430_LASTPOWERSTATEENTERED_MASK);
} }
static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
{ {
prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, omap2_prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
return 0; return 0;
...@@ -59,7 +59,7 @@ static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) ...@@ -59,7 +59,7 @@ static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{ {
prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, omap2_prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
OMAP4430_LASTPOWERSTATEENTERED_MASK, OMAP4430_LASTPOWERSTATEENTERED_MASK,
pwrdm->prcm_offs, OMAP4_PM_PWSTST); pwrdm->prcm_offs, OMAP4_PM_PWSTST);
return 0; return 0;
...@@ -70,7 +70,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) ...@@ -70,7 +70,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
u32 v; u32 v;
v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, omap2_prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
return 0; return 0;
...@@ -83,7 +83,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, ...@@ -83,7 +83,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
OMAP4_PM_PWSTCTRL); OMAP4_PM_PWSTCTRL);
return 0; return 0;
...@@ -96,7 +96,7 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, ...@@ -96,7 +96,7 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
m = omap2_pwrdm_get_mem_bank_retst_mask(bank); m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
OMAP4_PM_PWSTCTRL); OMAP4_PM_PWSTCTRL);
return 0; return 0;
...@@ -104,14 +104,15 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, ...@@ -104,14 +104,15 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
OMAP4430_LOGICSTATEST_MASK); OMAP4430_LOGICSTATEST_MASK);
} }
static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
{ {
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP4430_LOGICRETSTATE_MASK); OMAP4_PM_PWSTCTRL,
OMAP4430_LOGICRETSTATE_MASK);
} }
static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
...@@ -120,7 +121,8 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) ...@@ -120,7 +121,8 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
m = omap2_pwrdm_get_mem_bank_stst_mask(bank); m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, m); return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
m);
} }
static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
...@@ -129,7 +131,8 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) ...@@ -129,7 +131,8 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
m = omap2_pwrdm_get_mem_bank_retst_mask(bank); m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, m); return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP4_PM_PWSTCTRL, m);
} }
static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
...@@ -143,7 +146,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) ...@@ -143,7 +146,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
*/ */
/* XXX Is this udelay() value meaningful? */ /* XXX Is this udelay() value meaningful? */
while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) & while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) &
OMAP_INTRANSITION_MASK) && OMAP_INTRANSITION_MASK) &&
(c++ < PWRDM_TRANSITION_BAILOUT)) (c++ < PWRDM_TRANSITION_BAILOUT))
udelay(1); udelay(1);
......
...@@ -17,7 +17,8 @@ ...@@ -17,7 +17,8 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/io.h>
...@@ -30,10 +31,9 @@ ...@@ -30,10 +31,9 @@
#include "clock.h" #include "clock.h"
#include "clock2xxx.h" #include "clock2xxx.h"
#include "cm2xxx_3xxx.h" #include "cm2xxx_3xxx.h"
#include "cm44xx.h"
#include "prm2xxx_3xxx.h" #include "prm2xxx_3xxx.h"
#include "prm44xx.h" #include "prm44xx.h"
#include "prcm44xx.h" #include "prminst44xx.h"
#include "prm-regbits-24xx.h" #include "prm-regbits-24xx.h"
#include "prm-regbits-44xx.h" #include "prm-regbits-44xx.h"
#include "control.h" #include "control.h"
...@@ -48,9 +48,9 @@ u32 omap_prcm_get_reset_sources(void) ...@@ -48,9 +48,9 @@ u32 omap_prcm_get_reset_sources(void)
{ {
/* XXX This presumably needs modification for 34XX */ /* XXX This presumably needs modification for 34XX */
if (cpu_is_omap24xx() || cpu_is_omap34xx()) if (cpu_is_omap24xx() || cpu_is_omap34xx())
return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
if (cpu_is_omap44xx()) if (cpu_is_omap44xx())
return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
return 0; return 0;
} }
...@@ -75,9 +75,9 @@ void omap_prcm_arch_reset(char mode, const char *cmd) ...@@ -75,9 +75,9 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
} }
/* XXX should be moved to some OMAP2/3 specific code */ /* XXX should be moved to some OMAP2/3 specific code */
prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
OMAP2_RM_RSTCTRL); OMAP2_RM_RSTCTRL);
prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
} }
/** /**
......
...@@ -25,49 +25,49 @@ ...@@ -25,49 +25,49 @@
#include "prm-regbits-24xx.h" #include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h" #include "prm-regbits-34xx.h"
u32 prm_read_mod_reg(s16 module, u16 idx) u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{ {
return __raw_readl(prm_base + module + idx); return __raw_readl(prm_base + module + idx);
} }
void prm_write_mod_reg(u32 val, s16 module, u16 idx) void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{ {
__raw_writel(val, prm_base + module + idx); __raw_writel(val, prm_base + module + idx);
} }
/* Read-modify-write a register in a PRM module. Caller must lock */ /* Read-modify-write a register in a PRM module. Caller must lock */
u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{ {
u32 v; u32 v;
v = prm_read_mod_reg(module, idx); v = omap2_prm_read_mod_reg(module, idx);
v &= ~mask; v &= ~mask;
v |= bits; v |= bits;
prm_write_mod_reg(v, module, idx); omap2_prm_write_mod_reg(v, module, idx);
return v; return v;
} }
/* Read a PRM register, AND it, and shift the result down to bit 0 */ /* Read a PRM register, AND it, and shift the result down to bit 0 */
u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{ {
u32 v; u32 v;
v = prm_read_mod_reg(domain, idx); v = omap2_prm_read_mod_reg(domain, idx);
v &= mask; v &= mask;
v >>= __ffs(mask); v >>= __ffs(mask);
return v; return v;
} }
u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{ {
return prm_rmw_mod_reg_bits(bits, bits, module, idx); return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
} }
u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{ {
return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
} }
...@@ -86,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) ...@@ -86,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
return -EINVAL; return -EINVAL;
return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
(1 << shift)); (1 << shift));
} }
...@@ -110,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) ...@@ -110,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
return -EINVAL; return -EINVAL;
mask = 1 << shift; mask = 1 << shift;
prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
return 0; return 0;
} }
...@@ -140,15 +140,15 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) ...@@ -140,15 +140,15 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
mask = 1 << shift; mask = 1 << shift;
/* Check the current status to avoid de-asserting the line twice */ /* Check the current status to avoid de-asserting the line twice */
if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
return -EEXIST; return -EEXIST;
/* Clear the reset status by writing 1 to the status bit */ /* Clear the reset status by writing 1 to the status bit */
prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
/* de-assert the reset control line */ /* de-assert the reset control line */
prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
/* wait the status to be set */ /* wait the status to be set */
omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
mask), mask),
MAX_MODULE_HARDRESET_WAIT, c); MAX_MODULE_HARDRESET_WAIT, c);
......
...@@ -230,12 +230,12 @@ ...@@ -230,12 +230,12 @@
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
/* Power/reset management domain register get/set */ /* Power/reset management domain register get/set */
extern u32 prm_read_mod_reg(s16 module, u16 idx); extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
extern u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
extern u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
extern u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
/* These omap2_ PRM functions apply to both OMAP2 and 3 */ /* These omap2_ PRM functions apply to both OMAP2 and 3 */
extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
......
...@@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) ...@@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
m_type = omap2xxx_sdrc_get_type(); m_type = omap2xxx_sdrc_get_type();
local_irq_save(flags); local_irq_save(flags);
/*
* XXX These calls should be abstracted out through a
* prm2xxx.c function
*/
if (cpu_is_omap2420()) if (cpu_is_omap2420())
__raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
else else
......
...@@ -490,6 +490,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) ...@@ -490,6 +490,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
u32 wk_mask = 0; u32 wk_mask = 0;
u32 padconf = 0; u32 padconf = 0;
/* XXX These PRM accesses do not belong here */
uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
switch (uart->num) { switch (uart->num) {
......
...@@ -236,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp) ...@@ -236,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
* Sidetone uses McBSP ICLK - which must not idle when sidetones * Sidetone uses McBSP ICLK - which must not idle when sidetones
* are enabled or sidetones start sounding ugly. * are enabled or sidetones start sounding ugly.
*/ */
w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
w &= ~(1 << (mcbsp->id - 2)); w &= ~(1 << (mcbsp->id - 2));
cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
/* Enable McBSP Sidetone */ /* Enable McBSP Sidetone */
w = MCBSP_READ(mcbsp, SSELCR); w = MCBSP_READ(mcbsp, SSELCR);
...@@ -265,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp) ...@@ -265,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
w = MCBSP_READ(mcbsp, SSELCR); w = MCBSP_READ(mcbsp, SSELCR);
MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
w |= 1 << (mcbsp->id - 2); w |= 1 << (mcbsp->id - 2);
cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
} }
static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment