Commit c501d0b1 authored by Cristina Ciocan's avatar Cristina Ciocan Committed by Linus Walleij

pinctrl: baytrail: Add pin control operations

Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
  - function information (count, name and groups)
  - mux setting
  - gpio control (enable, disable, set direction)
- pin configuration:
  - pull disable
  - pull up/down and pull strength
  - debounce
  - any other option is treated as not supported.
Signed-off-by: default avatarCristina Ciocan <cristina.ciocan@intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent c8f5c4c7
...@@ -6,6 +6,9 @@ config PINCTRL_BAYTRAIL ...@@ -6,6 +6,9 @@ config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control" bool "Intel Baytrail GPIO pin control"
depends on GPIOLIB && ACPI depends on GPIOLIB && ACPI
select GPIOLIB_IRQCHIP select GPIOLIB_IRQCHIP
select PINMUX
select PINCONF
select GENERIC_PINCONF
help help
driver for memory mapped GPIO functionality on Intel Baytrail driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios. platforms. Supports 3 banks with 102, 28 and 44 gpios.
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