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Commit c655479a authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-soc3-for-v3.14' of... 

Merge tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Third Round of Renesas ARM Based SoC Updates for v3.14

* Global
  - Don't set plat_sci_port scbrr_algo_id field
  - Declare SCIF register base and IRQ as resources
  - Don't define SCIF platform data in an array
  - Use macros to declare SCIF devices

* r7s72100 SoC (RZ/A1H)
  - Add i2c clocks

* r8a7778 (R-Car M1)
  - Add sound SCU clock support

* tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
  arm: shmobile: r7s72100: add i2c clocks
  ARM: shmobile: r8a7791: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7779: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7790: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7740: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a73a4: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7778: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r7s72100: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: sh73a0: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7790: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7791: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7778: Declare SCIF register base and IRQ as resources
  ARM: shmobile: sh7372: Don't set plat_sci_port scbrr_algo_id field
  ARM: shmobile: r8a7779: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7740: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a73a4: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r7s72100: Declare SCIF register base and IRQ as resources
  ARM: shmobile: sh73a0: Declare SCIF register base and IRQ as resources
  ARM: shmobile: sh7372: Declare SCIF register base and IRQ as resources
  ARM: shmobile: r8a7790: Don't define SCIF platform data in an array
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 63df151a d85bcfa9
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Showing with 512 additions and 967 deletions
arch/arm/mach-shmobile/clock-r7s72100.c
View file @ c655479a
......@@ -27,6 +27,7 @@
#define FRQCR2 0xfcfe0014
#define STBCR3 0xfcfe0420
#define STBCR4 0xfcfe0424
#define STBCR9 0xfcfe0438
#define PLL_RATE 30
......@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = {
| CLK_ENABLE_ON_INIT),
};
enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
enum { MSTP97, MSTP96, MSTP95, MSTP94,
MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
MSTP33, MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
[MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
[MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
[MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
......
arch/arm/mach-shmobile/clock-r8a7778.c
View file @ c655479a
......@@ -115,6 +115,8 @@ static struct clk *main_clks[] = {
};
enum {
MSTP531, MSTP530,
MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
MSTP331,
MSTP323, MSTP322, MSTP321,
MSTP311, MSTP310,
......@@ -129,6 +131,15 @@ enum {
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
[MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
[MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
[MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
[MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
[MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
[MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
[MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
[MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
[MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
......@@ -219,6 +230,15 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
};
void __init r8a7778_clock_init(void)
......
arch/arm/mach-shmobile/setup-r7s72100.c
View file @ c655479a
......@@ -28,36 +28,38 @@
#include <mach/r7s72100.h>
#include <asm/mach/arch.h>
#define SCIF_DATA(index, baseaddr, irq) \
[index] = { \
#define R7S72100_SCIF(index, baseaddr, irq) \
static const struct plat_sci_port scif##index##_platform_data = { \
.type = PORT_SCIF, \
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scbrr_algo_id = SCBRR_ALGO_2, \
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
SCSCR_REIE, \
.mapbase = baseaddr, \
.irqs = { irq + 1, irq + 2, irq + 3, irq }, \
}
enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 };
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq + 1), \
DEFINE_RES_IRQ(irq + 2), \
DEFINE_RES_IRQ(irq + 3), \
DEFINE_RES_IRQ(irq), \
} \
static const struct plat_sci_port scif[] __initconst = {
SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */
SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */
SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */
SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */
SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
};
R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
static inline void r7s72100_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
#define r7s72100_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static struct sh_timer_config mtu2_0_platform_data __initdata = {
......@@ -81,14 +83,14 @@ static struct resource mtu2_0_resources[] __initdata = {
void __init r7s72100_add_dt_devices(void)
{
r7s72100_register_scif(SCIF0);
r7s72100_register_scif(SCIF1);
r7s72100_register_scif(SCIF2);
r7s72100_register_scif(SCIF3);
r7s72100_register_scif(SCIF4);
r7s72100_register_scif(SCIF5);
r7s72100_register_scif(SCIF6);
r7s72100_register_scif(SCIF7);
r7s72100_register_scif(0);
r7s72100_register_scif(1);
r7s72100_register_scif(2);
r7s72100_register_scif(3);
r7s72100_register_scif(4);
r7s72100_register_scif(5);
r7s72100_register_scif(6);
r7s72100_register_scif(7);
r7s72100_register_mtu2(0);
}
......
arch/arm/mach-shmobile/setup-r8a73a4.c
View file @ c655479a
......@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
ARRAY_SIZE(pfc_resources));
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.mapbase = baseaddr, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scbrr_algo_id = SCBRR_ALGO_4, \
.irqs = SCIx_IRQ_MUXED(irq)
#define SCIFA_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
.scscr = _scscr, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
#define SCIFB_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define R8A73A4_SCIFA(index, baseaddr, irq) \
R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
index, baseaddr, irq)
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
#define R8A73A4_SCIFB(index, baseaddr, irq) \
R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
static const struct plat_sci_port scif[] = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
};
R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
static inline void r8a73a4_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
#define r8a73a4_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct renesas_irqc_config irqc0_data = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
......@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
void __init r8a73a4_add_dt_devices(void)
{
r8a73a4_register_scif(SCIFA0);
r8a73a4_register_scif(SCIFA1);
r8a73a4_register_scif(SCIFB0);
r8a73a4_register_scif(SCIFB1);
r8a73a4_register_scif(SCIFB2);
r8a73a4_register_scif(SCIFB3);
r8a73a4_register_scif(0);
r8a73a4_register_scif(1);
r8a73a4_register_scif(2);
r8a73a4_register_scif(3);
r8a73a4_register_scif(4);
r8a73a4_register_scif(5);
r8a7790_register_cmt(10);
}
......
arch/arm/mach-shmobile/setup-r8a7740.c
View file @ c655479a
......@@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = {
},
};
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(100)),
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(101)),
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(102)),
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(103)),
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(104)),
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(105)),
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
/* SCIFA6 */
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6cc0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(106)),
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
/* SCIFA7 */
static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xe6cd0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(107)),
};
static struct platform_device scif7_device = {
.name = "sh-sci",
.id = 7,
.dev = {
.platform_data = &scif7_platform_data,
},
};
/* SCIFB */
static struct plat_sci_port scifb_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = SCIx_IRQ_MUXED(gic_spi(108)),
};
/* SCIF */
#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scifb_device = {
.name = "sh-sci",
.id = 8,
.dev = {
.platform_data = &scifb_platform_data,
},
};
R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
/* CMT */
static struct sh_timer_config cmt10_platform_data = {
......@@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
&scif5_device,
&scif6_device,
&scif7_device,
&scifb_device,
&scif8_device,
&cmt10_device,
};
......@@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void)
rmobile_add_device_to_domain("A3SP", &scif5_device);
rmobile_add_device_to_domain("A3SP", &scif6_device);
rmobile_add_device_to_domain("A3SP", &scif7_device);
rmobile_add_device_to_domain("A3SP", &scifb_device);
rmobile_add_device_to_domain("A3SP", &scif8_device);
rmobile_add_device_to_domain("A3SP", &i2c1_device);
}
......
arch/arm/mach-shmobile/setup-r8a7778.c
View file @ c655479a
......@@ -44,24 +44,31 @@
#include <asm/hardware/cache-l2x0.h>
/* SCIF */
#define SCIF_INFO(baseaddr, irq) \
{ \
.mapbase = baseaddr, \
#define R8A7778_SCIF(index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
.scbrr_algo_id = SCBRR_ALGO_2, \
.type = PORT_SCIF, \
.irqs = SCIx_IRQ_MUXED(irq), \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
static struct plat_sci_port scif_platform_data[] __initdata = {
SCIF_INFO(0xffe40000, gic_iid(0x66)),
SCIF_INFO(0xffe41000, gic_iid(0x67)),
SCIF_INFO(0xffe42000, gic_iid(0x68)),
SCIF_INFO(0xffe43000, gic_iid(0x69)),
SCIF_INFO(0xffe44000, gic_iid(0x6a)),
SCIF_INFO(0xffe45000, gic_iid(0x6b)),
};
R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
#define r8a7778_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
/* TMU */
static struct resource sh_tmu0_resources[] __initdata = {
......@@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id)
void __init r8a7778_add_dt_devices(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
if (base) {
......@@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void)
}
#endif
for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
platform_device_register_data(&platform_bus, "sh-sci", i,
&scif_platform_data[i],
sizeof(struct plat_sci_port));
r8a7778_register_scif(0);
r8a7778_register_scif(1);
r8a7778_register_scif(2);
r8a7778_register_scif(3);
r8a7778_register_scif(4);
r8a7778_register_scif(5);
r8a7778_register_tmu(0);
r8a7778_register_tmu(1);
}
......
arch/arm/mach-shmobile/setup-r8a7779.c
View file @ c655479a
......@@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void)
ARRAY_SIZE(r8a7779_pinctrl_devices));
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xffe40000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xffe41000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xffe42000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xffe43000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xffe44000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xffe45000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
};
/* SCIF */
#define R8A7779_SCIF(index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = PORT_SCIF, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
/* TMU */
static struct sh_timer_config tmu00_platform_data = {
......
arch/arm/mach-shmobile/setup-r8a7790.c
View file @ c655479a
......@@ -100,61 +100,51 @@ void __init r8a7790_pinmux_init(void)
r8a7790_register_i2c(3);
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
.type = scif_type, \
.mapbase = baseaddr, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.irqs = SCIx_IRQ_MUXED(irq)
#define SCIFA_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
}
#define SCIFB_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define SCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_2, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define HSCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_6, \
.scscr = SCSCR_RE | SCSCR_TE, \
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = _scscr, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
HSCIF0, HSCIF1 };
static const struct plat_sci_port scif[] __initconst = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
};
static inline void r8a7790_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
#define R8A7790_SCIF(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
#define R8A7790_SCIFA(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
index, baseaddr, irq)
#define R8A7790_SCIFB(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
#define R8A7790_HSCIF(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
#define r8a7790_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct renesas_irqc_config irqc0_data __initconst = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
......@@ -207,16 +197,16 @@ static const struct resource cmt00_resources[] __initconst = {
void __init r8a7790_add_dt_devices(void)
{
r8a7790_register_scif(SCIFA0);
r8a7790_register_scif(SCIFA1);
r8a7790_register_scif(SCIFB0);
r8a7790_register_scif(SCIFB1);
r8a7790_register_scif(SCIFB2);
r8a7790_register_scif(SCIFA2);
r8a7790_register_scif(SCIF0);
r8a7790_register_scif(SCIF1);
r8a7790_register_scif(HSCIF0);
r8a7790_register_scif(HSCIF1);
r8a7790_register_scif(0);
r8a7790_register_scif(1);
r8a7790_register_scif(2);
r8a7790_register_scif(3);
r8a7790_register_scif(4);
r8a7790_register_scif(5);
r8a7790_register_scif(6);
r8a7790_register_scif(7);
r8a7790_register_scif(8);
r8a7790_register_scif(9);
r8a7790_register_cmt(00);
}
......
arch/arm/mach-shmobile/setup-r8a7791.c
View file @ c655479a
......@@ -84,66 +84,49 @@ void __init r8a7791_pinmux_init(void)
r8a7791_register_gpio(7);
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
.type = scif_type, \
.mapbase = baseaddr, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.irqs = SCIx_IRQ_MUXED(irq)
#define SCIFA_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define SCIFB_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define SCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_2, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define HSCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_6, \
.scscr = SCSCR_RE | SCSCR_TE, \
#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
static const struct plat_sci_port scif[] __initconst = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
};
static inline void r8a7791_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
#define R8A7791_SCIF(index, baseaddr, irq) \
__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
#define R8A7791_SCIFA(index, baseaddr, irq) \
__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
#define R8A7791_SCIFB(index, baseaddr, irq) \
__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
#define r8a7791_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct sh_timer_config cmt00_platform_data __initconst = {
.name = "CMT00",
......@@ -202,21 +185,21 @@ static const struct resource thermal_resources[] __initconst = {
void __init r8a7791_add_dt_devices(void)
{
r8a7791_register_scif(SCIFA0);
r8a7791_register_scif(SCIFA1);
r8a7791_register_scif(SCIFB0);
r8a7791_register_scif(SCIFB1);
r8a7791_register_scif(SCIFB2);
r8a7791_register_scif(SCIFA2);
r8a7791_register_scif(SCIF0);
r8a7791_register_scif(SCIF1);
r8a7791_register_scif(SCIF2);
r8a7791_register_scif(SCIF3);
r8a7791_register_scif(SCIF4);
r8a7791_register_scif(SCIF5);
r8a7791_register_scif(SCIFA3);
r8a7791_register_scif(SCIFA4);
r8a7791_register_scif(SCIFA5);
r8a7791_register_scif(0);
r8a7791_register_scif(1);
r8a7791_register_scif(2);
r8a7791_register_scif(3);
r8a7791_register_scif(4);
r8a7791_register_scif(5);
r8a7791_register_scif(6);
r8a7791_register_scif(7);
r8a7791_register_scif(8);
r8a7791_register_scif(9);
r8a7791_register_scif(10);
r8a7791_register_scif(11);
r8a7791_register_scif(12);
r8a7791_register_scif(13);
r8a7791_register_scif(14);
r8a7791_register_cmt(00);
}
......
arch/arm/mach-shmobile/setup-sh7372.c
View file @ c655479a
......@@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void)
platform_device_register(&sh7372_pfc_device);
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
evt2irq(0x0c00), evt2irq(0x0c00) },
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
evt2irq(0x0c20), evt2irq(0x0c20) },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
evt2irq(0x0c40), evt2irq(0x0c40) },
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
evt2irq(0x0c60), evt2irq(0x0c60) },
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
evt2irq(0x0d20), evt2irq(0x0d20) },
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
evt2irq(0x0d40), evt2irq(0x0d40) },
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
/* SCIFB */
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
evt2irq(0x0d60), evt2irq(0x0d60) },
};
/* SCIF */
#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
/* CMT */
static struct sh_timer_config cmt2_platform_data = {
......
arch/arm/mach-shmobile/setup-sh73a0.c
View file @ c655479a
......@@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void)
ARRAY_SIZE(pfc_resources));
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(72), gic_spi(72),
gic_spi(72), gic_spi(72) },
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(73), gic_spi(73),
gic_spi(73), gic_spi(73) },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(74), gic_spi(74),
gic_spi(74), gic_spi(74) },
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(75), gic_spi(75),
gic_spi(75), gic_spi(75) },
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(78), gic_spi(78),
gic_spi(78), gic_spi(78) },
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(79), gic_spi(79),
gic_spi(79), gic_spi(79) },
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6cc0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(156), gic_spi(156),
gic_spi(156), gic_spi(156) },
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xe6cd0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(143), gic_spi(143),
gic_spi(143), gic_spi(143) },
};
static struct platform_device scif7_device = {
.name = "sh-sci",
.id = 7,
.dev = {
.platform_data = &scif7_platform_data,
},
};
static struct plat_sci_port scif8_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = { gic_spi(80), gic_spi(80),
gic_spi(80), gic_spi(80) },
};
/* SCIF */
#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif8_device = {
.name = "sh-sci",
.id = 8,
.dev = {
.platform_data = &scif8_platform_data,
},
};
SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
static struct sh_timer_config cmt10_platform_data = {
.name = "CMT10",
......
drivers/tty/serial/sh-sci.c
View file @ c655479a
This diff is collapsed.
drivers/tty/serial/sh-sci.h
View file @ c655479a
......@@ -9,7 +9,7 @@
#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask)
#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
......
include/linux/serial_sci.h
View file @ c655479a
......@@ -11,11 +11,11 @@
#define SCIx_NOT_SUPPORTED (-1)
enum {
SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
SCBRR_ALGO_1, /* clk / (16 * bps) */
SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
SCBRR_ALGO_3, /* clk / (8 * bps) */
SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
};
......@@ -70,17 +70,6 @@ enum {
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
};
/* Offsets into the sci_port->gpios array */
enum {
SCIx_SCK,
SCIx_RXD,
SCIx_TXD,
SCIx_CTS,
SCIx_RTS,
SCIx_NR_FNS,
};
enum {
SCIx_PROBE_REGTYPE,
......@@ -108,10 +97,10 @@ enum {
}
#define SCIx_IRQ_IS_MUXED(port) \
((port)->cfg->irqs[SCIx_ERI_IRQ] == \
(port)->cfg->irqs[SCIx_RXI_IRQ]) || \
((port)->cfg->irqs[SCIx_ERI_IRQ] && \
!(port)->cfg->irqs[SCIx_RXI_IRQ])
((port)->irqs[SCIx_ERI_IRQ] == \
(port)->irqs[SCIx_RXI_IRQ]) || \
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
/*
* SCI register subset common for all port types.
* Not all registers will exist on all parts.
......@@ -142,20 +131,17 @@ struct plat_sci_port_ops {
struct plat_sci_port {
unsigned long mapbase; /* resource base */
unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
upf_t flags; /* UPF_* flags */
unsigned long capabilities; /* Port features/capabilities */
unsigned int sampling_rate;
unsigned int scbrr_algo_id; /* SCBRR calculation algo */
unsigned int scscr; /* SCSCR initialization */
/*
* Platform overrides if necessary, defaults otherwise.
*/
int overrun_bit;
unsigned int error_mask;
int port_reg;
unsigned char regshift;
unsigned char regtype;
......
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