[AGP] Remove bogus AGP/DRM assumptions

[Forward port of a 2.4 patch that got applied last month -- DJ] 
 
AGP/DRM currently assume that GATT entries can be converted
to physical addresses with a simple mask.  Additionally, agpgart
assumes in a couple places that the mask is ~0xfff, i.e., that
all the GART control bits are in the low 12 bits.  Both assumptions
are bogus, so:
  
Make agp_memory.memory[] (exported from agpgart to DRM) contain physical
addresses, not GATT entries.
  
DRM assumes agp_memory contains GATT entries, and it converts them to
physical addresses with "paddr = agp_memory.memory[i] & mask".  460GX
requires both a shift and a mask, so exporting plain physical addresses
and a mask of ~0UL allows agpgart to add 460GX support without requiring
DRM interface changes.

drivers/char/agp/agp.h

@@ -133,6 +133,7 @@ struct agp_bridge_data {
 	u32 *gatt_table;
 	u32 *gatt_table_real;
 	unsigned long scratch_page;
+	unsigned long scratch_page_real;
 	unsigned long gart_bus_addr;
 	unsigned long gatt_bus_addr;
 	u32 mode;
@@ -145,7 +146,6 @@ struct agp_bridge_data {
 	int needs_scratch_page;
 	int aperture_size_idx;
 	int num_aperture_sizes;
-	int num_of_masks;
 	int capndx;
 	int cant_use_aperture;
 

drivers/char/agp/ali-agp.c

@@ -198,7 +198,6 @@ static struct aper_size_info_32 ali_generic_sizes[7] =
 static int __init ali_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = ali_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
 	agp_bridge.size_type = U32_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/amd-k7-agp.c

@@ -308,7 +308,8 @@ static int amd_insert_memory(agp_memory * mem,
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 		addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
 		cur_gatt = GET_GATT(addr);
-		cur_gatt[GET_GATT_OFF(addr)] = mem->memory[i];
+		cur_gatt[GET_GATT_OFF(addr)] =
+			agp_bridge.mask_memory(mem->memory[i], mem->type);
 	}
 	agp_bridge.tlb_flush(mem);
 	return 0;
@@ -354,7 +355,6 @@ static struct gatt_mask amd_irongate_masks[] =
 static int __init amd_irongate_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = amd_irongate_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) amd_irongate_sizes;
 	agp_bridge.size_type = LVL2_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/amd-k8-agp.c

@@ -81,7 +81,7 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
 	}
 
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
-		addr = mem->memory[i];
+		addr = agp_bridge.mask_memory(mem->memory[i], mem->type);
 
 		tmp = addr;
 		BUG_ON(tmp & 0xffffff0000000ffc);
@@ -446,7 +446,6 @@ static void agp_x86_64_agp_enable(u32 mode)
 static int __init amd_8151_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = amd_8151_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) amd_8151_sizes;
 	agp_bridge.size_type = U32_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/backend.c

@@ -123,8 +123,9 @@ static int agp_backend_initialize(struct pci_dev *dev)
 			printk(KERN_ERR PFX "unable to get memory for scratch page.\n");
 			return -ENOMEM;
 		}
-		agp_bridge.scratch_page = virt_to_phys(addr);
-		agp_bridge.scratch_page = agp_bridge.mask_memory(agp_bridge.scratch_page, 0);
+		agp_bridge.scratch_page_real = virt_to_phys(addr);
+		agp_bridge.scratch_page =
+			agp_bridge.mask_memory(agp_bridge.scratch_page_real, 0);
 	}
 
 	size_value = agp_bridge.fetch_size();
@@ -165,8 +166,7 @@ static int agp_backend_initialize(struct pci_dev *dev)
 
 err_out:
 	if (agp_bridge.needs_scratch_page == TRUE) {
-		agp_bridge.scratch_page &= ~(0x00000fff);
-		agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page));
+		agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
 	}
 	if (got_gatt)
 		agp_bridge.free_gatt_table();
@@ -184,8 +184,7 @@ static void agp_backend_cleanup(void)
 	vfree(agp_bridge.key_list);
 
 	if (agp_bridge.needs_scratch_page == TRUE) {
-		agp_bridge.scratch_page &= ~(0x00000fff);
-		agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page));
+		agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
 	}
 }
 

drivers/char/agp/generic.c

@@ -110,7 +110,6 @@ void agp_free_memory(agp_memory * curr)
 	}
 	if (curr->page_count != 0) {
 		for (i = 0; i < curr->page_count; i++) {
-			curr->memory[i] &= ~(0x00000fff);
 			agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[i]));
 		}
 	}
@@ -158,7 +157,7 @@ agp_memory *agp_allocate_memory(size_t page_count, u32 type)
 			agp_free_memory(new);
 			return NULL;
 		}
-		new->memory[i] = agp_bridge.mask_memory(virt_to_phys(addr), type);
+		new->memory[i] = virt_to_phys((void *) new->memory[i]);
 		new->page_count++;
 	}
 
@@ -241,9 +240,6 @@ int agp_num_entries(void)
 
 int agp_copy_info(agp_kern_info * info)
 {
-	unsigned long page_mask = 0;
-	int i;
-
 	memset(info, 0, sizeof(agp_kern_info));
 	if (agp_bridge.type == NOT_SUPPORTED) {
 		info->chipset = agp_bridge.type;
@@ -259,11 +255,7 @@ int agp_copy_info(agp_kern_info * info)
 	info->max_memory = agp_bridge.max_memory_agp;
 	info->current_memory = atomic_read(&agp_bridge.current_memory_agp);
 	info->cant_use_aperture = agp_bridge.cant_use_aperture;
-
-	for(i = 0; i < agp_bridge.num_of_masks; i++)
-		page_mask |= agp_bridge.mask_memory(page_mask, i);
-
-	info->page_mask = ~page_mask;
+	info->page_mask = ~0UL;
 	return 0;
 }
 
@@ -640,7 +632,8 @@ int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type)
 	}
 
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
-		agp_bridge.gatt_table[j] = mem->memory[i];
+		agp_bridge.gatt_table[j] =
+				agp_bridge.mask_memory(mem->memory[i], mem->type);
 
 	agp_bridge.tlb_flush(mem);
 	return 0;

drivers/char/agp/hp-agp.c

@@ -331,7 +331,6 @@ static unsigned long hp_zx1_mask_memory(unsigned long addr, int type)
 static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
 {
 	agp_bridge.masks = hp_zx1_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.dev_private_data = NULL;
 	agp_bridge.size_type = FIXED_APER_SIZE;
 	agp_bridge.needs_scratch_page = FALSE;

drivers/char/agp/i460-agp.c

@@ -525,7 +525,6 @@ static unsigned long i460_mask_memory (unsigned long addr, int type)
 
 static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
 {
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.masks = i460_masks;
 	agp_bridge.aperture_sizes = (void *) i460_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;

drivers/char/agp/i7x05-agp.c

@@ -96,7 +96,6 @@ static void i7505_setup (u32 mode)
 static int __init intel_7505_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_7505_sizes;
 	agp_bridge.size_type = U16_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/intel-agp.c

@@ -153,7 +153,8 @@ static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
 	CACHE_FLUSH();
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 		OUTREG32(intel_i810_private.registers,
-			 I810_PTE_BASE + (j * 4), mem->memory[i]);
+			I810_PTE_BASE + (j * 4),
+			agp_bridge.mask_memory(mem->memory[i], mem->type));
 	}
 	CACHE_FLUSH();
 
@@ -219,7 +220,7 @@ static agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 			agp_free_memory(new);
 			return NULL;
 		}
-		new->memory[0] = agp_bridge.mask_memory(virt_to_phys(addr), type);
+		new->memory[0] = virt_to_phys((void *) new->memory[0]);
 		new->page_count = 1;
 		new->num_scratch_pages = 1;
 		new->type = AGP_PHYS_MEMORY;
@@ -251,7 +252,6 @@ static int __init intel_i810_setup(struct pci_dev *i810_dev)
 	intel_i810_private.i810_dev = i810_dev;
 
 	agp_bridge.masks = intel_i810_masks;
-	agp_bridge.num_of_masks = 2;
 	agp_bridge.aperture_sizes = (void *) intel_i810_sizes;
 	agp_bridge.size_type = FIXED_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 2;
@@ -454,7 +454,8 @@ static int intel_i830_insert_entries(agp_memory *mem,off_t pg_start,int type)
 	CACHE_FLUSH();
 
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
-		OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4),mem->memory[i]);
+		OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4),
+			agp_bridge.mask_memory(mem->memory[i], mem->type));
 
 	CACHE_FLUSH();
 
@@ -514,7 +515,7 @@ static agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 			return(NULL);
 		}
 
-		nw->memory[0] = agp_bridge.mask_memory(virt_to_phys(addr),type);
+		nw->memory[0] = virt_to_phys((void *) nw->memory[0]);
 		nw->page_count = 1;
 		nw->num_scratch_pages = 1;
 		nw->type = AGP_PHYS_MEMORY;
@@ -530,7 +531,6 @@ static int __init intel_i830_setup(struct pci_dev *i830_dev)
 	intel_i830_private.i830_dev = i830_dev;
 
 	agp_bridge.masks = intel_i810_masks;
-	agp_bridge.num_of_masks = 3;
 	agp_bridge.aperture_sizes = (void *) intel_i830_sizes;
 	agp_bridge.size_type = FIXED_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 2;
@@ -974,7 +974,6 @@ static struct aper_size_info_8 intel_830mp_sizes[4] =
 static int __init intel_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_generic_sizes;
 	agp_bridge.size_type = U16_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;
@@ -1004,7 +1003,6 @@ static int __init intel_generic_setup (struct pci_dev *pdev)
 static int __init intel_815_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_815_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 2;
@@ -1035,7 +1033,6 @@ static int __init intel_815_setup (struct pci_dev *pdev)
 static int __init intel_820_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;
@@ -1065,7 +1062,6 @@ static int __init intel_820_setup (struct pci_dev *pdev)
 static int __init intel_830mp_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_830mp_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 4;
@@ -1095,7 +1091,6 @@ static int __init intel_830mp_setup (struct pci_dev *pdev)
 static int __init intel_840_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;
@@ -1125,7 +1120,6 @@ static int __init intel_840_setup (struct pci_dev *pdev)
 static int __init intel_845_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;
@@ -1155,7 +1149,6 @@ static int __init intel_845_setup (struct pci_dev *pdev)
 static int __init intel_850_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;
@@ -1185,7 +1178,6 @@ static int __init intel_850_setup (struct pci_dev *pdev)
 static int __init intel_860_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/sis-agp.c

@@ -89,7 +89,6 @@ static struct gatt_mask sis_generic_masks[] =
 static int __init sis_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = sis_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/sworks-agp.c

@@ -363,7 +363,8 @@ static int serverworks_insert_memory(agp_memory * mem,
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 		addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
 		cur_gatt = SVRWRKS_GET_GATT(addr);
-		cur_gatt[GET_GATT_OFF(addr)] = mem->memory[i];
+		cur_gatt[GET_GATT_OFF(addr)] =
+			agp_bridge.mask_memory(mem->memory[i], mem->type);
 	}
 	agp_bridge.tlb_flush(mem);
 	return 0;
@@ -520,7 +521,6 @@ static int __init serverworks_setup (struct pci_dev *pdev)
 	serverworks_private.svrwrks_dev = pdev;
 
 	agp_bridge.masks = serverworks_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) serverworks_sizes;
 	agp_bridge.size_type = LVL2_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/via-agp.c

@@ -97,7 +97,6 @@ static struct gatt_mask via_generic_masks[] =
 static int __init via_generic_setup (struct pci_dev *pdev)
 {
 	agp_bridge.masks = via_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) via_generic_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;

drivers/char/agp/via-kt400.c

@@ -122,7 +122,6 @@ static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id
 	agp_bridge.type = VIA_APOLLO_KT400_3;
 	agp_bridge.capndx = cap_ptr;
 	agp_bridge.masks = via_generic_masks;
-	agp_bridge.num_of_masks = 1;
 	agp_bridge.aperture_sizes = (void *) via_generic_sizes;
 	agp_bridge.size_type = U8_APER_SIZE;
 	agp_bridge.num_aperture_sizes = 7;