[ARM] Place initial data/code in assembly into the correct section

We were mixing some data and code in the processor support assembly
files.  Place the correct objects into their respective sections.

arch/arm/mm/cache-v3.S

@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -107,6 +108,9 @@ ENTRY(v3_dma_flush_range)
 ENTRY(v3_dma_clean_range)
 	mov	pc, lr
 
+	__INITDATA
+
+	.type	v3_cache_fns, #object
 ENTRY(v3_cache_fns)
 	.long	v3_flush_kern_cache_all
 	.long	v3_flush_user_cache_all
@@ -116,3 +120,4 @@ ENTRY(v3_cache_fns)
 	.long	v3_dma_inv_range
 	.long	v3_dma_clean_range
 	.long	v3_dma_flush_range
+	.size	v3_cache_fns, . - v3_cache_fns

arch/arm/mm/cache-v4.S

@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -109,6 +110,9 @@ ENTRY(v4_dma_flush_range)
 ENTRY(v4_dma_clean_range)
 	mov	pc, lr
 
+	__INITDATA
+
+	.type	v4_cache_fns, #object
 ENTRY(v4_cache_fns)
 	.long	v4_flush_kern_cache_all
 	.long	v4_flush_user_cache_all
@@ -118,3 +122,4 @@ ENTRY(v4_cache_fns)
 	.long	v4_dma_inv_range
 	.long	v4_dma_clean_range
 	.long	v4_dma_flush_range
+	.size	v4_cache_fns, . - v4_cache_fns

arch/arm/mm/cache-v4wb.S

@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -185,6 +186,9 @@ ENTRY(v4wb_dma_clean_range)
 	.globl	v4wb_dma_flush_range
 	.set	v4wb_dma_flush_range, v4wb_coherent_kern_range
 
+	__INITDATA
+
+	.type	v4wb_cache_fns, #object
 ENTRY(v4wb_cache_fns)
 	.long	v4wb_flush_kern_cache_all
 	.long	v4wb_flush_user_cache_all
@@ -194,3 +198,4 @@ ENTRY(v4wb_cache_fns)
 	.long	v4wb_dma_inv_range
 	.long	v4wb_dma_clean_range
 	.long	v4wb_dma_flush_range
+	.size	v4wb_cache_fns, . - v4wb_cache_fns

arch/arm/mm/cache-v4wt.S

@@ -12,6 +12,7 @@
  *  We assume that the write buffer is not enabled.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -158,6 +159,9 @@ ENTRY(v4wt_dma_clean_range)
 	.globl	v4wt_dma_flush_range
 	.equ	v4wt_dma_flush_range, v4wt_dma_inv_range
 
+	__INITDATA
+
+	.type	v4wt_cache_fns, #object
 ENTRY(v4wt_cache_fns)
 	.long	v4wt_flush_kern_cache_all
 	.long	v4wt_flush_user_cache_all
@@ -167,4 +171,4 @@ ENTRY(v4wt_cache_fns)
 	.long	v4wt_dma_inv_range
 	.long	v4wt_dma_clean_range
 	.long	v4wt_dma_flush_range
-
+	.size	v4wt_cache_fns, . - v4wt_cache_fns

arch/arm/mm/copypage-v3.S

@@ -58,8 +58,10 @@ ENTRY(v3_clear_user_page)
 	bne	1b				@ 1
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v3_user_fns, #object
 ENTRY(v3_user_fns)
 	.long	v3_clear_user_page
 	.long	v3_copy_user_page
+	.size	v3_user_fns, . - v3_user_fns

arch/arm/mm/copypage-v4mc.S

@@ -71,9 +71,10 @@ ENTRY(v4_mc_clear_user_page)
 	bne	1b				@ 1
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v4_mc_user_fns, #object
 ENTRY(v4_mc_user_fns)
 	.long	v4_mc_clear_user_page
 	.long	v4_mc_copy_user_page
-
+	.size	v4_mc_user_fns, . - v4_mc_user_fns

arch/arm/mm/copypage-v4wb.S

@@ -70,9 +70,10 @@ ENTRY(v4wb_clear_user_page)
 	mcr	p15, 0, r1, c7, c10, 4		@ 1   drain WB
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v4wb_user_fns, #object
 ENTRY(v4wb_user_fns)
 	.long	v4wb_clear_user_page
 	.long	v4wb_copy_user_page
-
+	.size	v4wb_user_fns, . - v4wb_user_fns

arch/arm/mm/copypage-v4wt.S

@@ -64,9 +64,10 @@ ENTRY(v4wt_clear_user_page)
 	mcr	p15, 0, r2, c7, c7, 0		@ flush ID cache
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v4wt_user_fns, #object
 ENTRY(v4wt_user_fns)
 	.long	v4wt_clear_user_page
 	.long	v4wt_copy_user_page
-
+	.size	v4wt_user_fns, . - v4wt_user_fns

arch/arm/mm/copypage-xscale.S

@@ -104,8 +104,10 @@ ENTRY(xscale_mc_clear_user_page)
 	bne	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
+	.type	xscale_mc_user_fns, #object
 ENTRY(xscale_mc_user_fns)
 	.long	xscale_mc_clear_user_page
 	.long	xscale_mc_copy_user_page
+	.size	xscale_mc_user_fns, . - xscale_mc_user_fns

arch/arm/mm/proc-arm1020.S

@@ -409,31 +409,9 @@ ENTRY(cpu_arm1020_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm1020_name)
-	.ascii	"ARM1020"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
-	.ascii	"B"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-	.ascii	"RR"
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm1020_setup, #function
 __arm1020_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -467,8 +445,9 @@ __arm1020_setup:
 	orr	r0, r0, #0x1000 		@ I Cache on
 #endif
 	mov	pc, lr
+	.size	__arm1020_setup, . - __arm1020_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -484,9 +463,10 @@ arm1020_processor_functions:
 	.word	cpu_arm1020_dcache_clean_area
 	.word	cpu_arm1020_switch_mm
 	.word	cpu_arm1020_set_pte
-
 	.size	arm1020_processor_functions, . - arm1020_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5t"
@@ -496,6 +476,30 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm1020_name, #object
+cpu_arm1020_name:
+	.ascii	"ARM1020"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+#ifndef CONFIG_CPU_BPREDICT_DISABLE
+	.ascii	"B"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+	.ascii	"RR"
+#endif
+	.ascii	"\0"
+	.size	cpu_arm1020_name, . - cpu_arm1020_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm1020e.S

@@ -392,31 +392,9 @@ ENTRY(cpu_arm1020e_set_pte)
 #endif
 	mov	pc, lr
 
-
-ENTRY(cpu_arm1020e_name)
-	.ascii	"ARM1020E"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
-	.ascii	"B"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-	.ascii	"RR"
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm1020e_setup, #function
 __arm1020e_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -450,8 +428,9 @@ __arm1020e_setup:
 	orr	r0, r0, #0x1000 		@ I Cache on
 #endif
 	mov	pc, lr
+	.size	__arm1020e_setup, . - __arm1020e_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -467,9 +446,10 @@ arm1020e_processor_functions:
 	.word	cpu_arm1020e_dcache_clean_area
 	.word	cpu_arm1020e_switch_mm
 	.word	cpu_arm1020e_set_pte
-
 	.size	arm1020e_processor_functions, . - arm1020e_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5te"
@@ -479,6 +459,30 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm1020e_name, #object
+cpu_arm1020e_name:
+	.ascii	"ARM1020E"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+#ifndef CONFIG_CPU_BPREDICT_DISABLE
+	.ascii	"B"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+	.ascii	"RR"
+#endif
+	.ascii	"\0"
+	.size	cpu_arm1020e_name, . - cpu_arm1020e_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm1022.S

@@ -372,31 +372,9 @@ ENTRY(cpu_arm1022_set_pte)
 #endif
 	mov	pc, lr
 
-
-ENTRY(cpu_arm1022_name)
-	.ascii	"arm1022"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
-	.ascii	"B"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-	.ascii	"RR"
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm1022_setup, #function
 __arm1022_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -430,8 +408,9 @@ __arm1022_setup:
 	orr	r0, r0, #0x1000 		@ ...I............
 #endif
 	mov	pc, lr
+	.size	__arm1022_setup, . - __arm1022_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -447,9 +426,10 @@ arm1022_processor_functions:
 	.word	cpu_arm1022_dcache_clean_area
 	.word	cpu_arm1022_switch_mm
 	.word	cpu_arm1022_set_pte
-
 	.size	arm1022_processor_functions, . - arm1022_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5te"
@@ -459,6 +439,30 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm1022_name, #object
+cpu_arm1022_name:
+	.ascii	"arm1022"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+#ifndef CONFIG_CPU_BPREDICT_DISABLE
+	.ascii	"B"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+	.ascii	"RR"
+#endif
+	.ascii	"\0"
+	.size	cpu_arm1022_name, . - cpu_arm1022_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm1026.S

@@ -365,6 +365,7 @@ ENTRY(cpu_arm1026_set_pte)
 
 	__INIT
 
+	.type	__arm1026_setup, #function
 __arm1026_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -402,6 +403,9 @@ __arm1026_setup:
 	orr	r0, r0, #0x1000 		@ ...I............
 #endif
 	mov	pc, lr
+	.size	__arm1026_setup, . - __arm1026_setup
+
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -409,7 +413,7 @@ __arm1026_setup:
  */
 	.type	arm1026_processor_functions, #object
 arm1026_processor_functions:
-	.word	ev5t_early_abort
+	.word	v5t_early_abort
 	.word	cpu_arm1026_proc_init
 	.word	cpu_arm1026_proc_fin
 	.word	cpu_arm1026_reset
@@ -417,7 +421,6 @@ arm1026_processor_functions:
 	.word	cpu_arm1026_dcache_clean_area
 	.word	cpu_arm1026_switch_mm
 	.word	cpu_arm1026_set_pte
-
 	.size	arm1026_processor_functions, . - arm1026_processor_functions
 
 	.section .rodata
@@ -434,7 +437,7 @@ cpu_elf_name:
 	.align
 
 	.type	cpu_arm1026_name, #object
-ENTRY(cpu_arm1026_name)
+cpu_arm1026_name:
 	.ascii	"ARM1026EJ-S"
 #ifndef CONFIG_CPU_ICACHE_DISABLE
 	.ascii	"i"
@@ -454,9 +457,10 @@ ENTRY(cpu_arm1026_name)
 	.ascii	"RR"
 #endif
 	.ascii	"\0"
-	.align
 	.size	cpu_arm1026_name, . - cpu_arm1026_name
 
+	.align
+
 	.section ".proc.info", #alloc, #execinstr
 
 	.type	__arm1026_proc_info,#object

arch/arm/mm/proc-arm6_7.S

@@ -247,16 +247,9 @@ ENTRY(cpu_arm7_reset)
 		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc
 		mov	pc, r0
 
-cpu_arm6_name:	.asciz	"ARM6"
-cpu_arm610_name:
-		.asciz	"ARM610"
-cpu_arm7_name:	.asciz	"ARM7"
-cpu_arm710_name:
-		.asciz	"ARM710"
-		.align
-
 		__INIT
 
+		.type	__arm6_setup, #function
 __arm6_setup:	mov	r0, #0
 		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
 		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
@@ -266,7 +259,9 @@ __arm6_setup:	mov	r0, #0
 		mov	r0, #0x3d			@ . ..RS BLDP WCAM
 		orr	r0, r0, #0x100			@ . ..01 0011 1101
 		mov	pc, lr
+		.size	__arm6_setup, . - __arm6_setup
 
+		.type	__arm7_setup, #function
 __arm7_setup:	mov	r0, #0
 		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
 		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
@@ -276,6 +271,9 @@ __arm7_setup:	mov	r0, #0
 		mov	r0, #0x7d			@ . ..RS BLDP WCAM
 		orr	r0, r0, #0x100			@ . ..01 0111 1101
 		mov	pc, lr
+		.size	__arm7_setup, . - __arm7_setup
+
+		__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -309,6 +307,8 @@ ENTRY(arm7_processor_functions)
 		.word	cpu_arm7_set_pte
 		.size	arm7_processor_functions, . - arm7_processor_functions
 
+		.section ".rodata"
+
 		.type	cpu_arch_name, #object
 cpu_arch_name:	.asciz	"armv3"
 		.size	cpu_arch_name, . - cpu_arch_name
@@ -316,6 +316,25 @@ cpu_arch_name:	.asciz	"armv3"
 		.type	cpu_elf_name, #object
 cpu_elf_name:	.asciz	"v3"
 		.size	cpu_elf_name, . - cpu_elf_name
+
+		.type	cpu_arm6_name, #object
+cpu_arm6_name:	.asciz	"ARM6"
+		.size	cpu_arm6_name, . - cpu_arm6_name
+
+		.type	cpu_arm610_name, #object
+cpu_arm610_name:
+		.asciz	"ARM610"
+		.size	cpu_arm610_name, . - cpu_arm610_name
+
+		.type	cpu_arm7_name, #object
+cpu_arm7_name:	.asciz	"ARM7"
+		.size	cpu_arm7_name, . - cpu_arm7_name
+
+		.type	cpu_arm710_name, #object
+cpu_arm710_name:
+		.asciz	"ARM710"
+		.size	cpu_arm710_name, . - cpu_arm710_name
+
 		.align
 
 		.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm720.S

@@ -124,13 +124,9 @@ ENTRY(cpu_arm720_reset)
 		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
 		mov	pc, r0
 
-	
-cpu_arm720_name:
-		.asciz	"ARM720T"
-		.align
-
 		__INIT
 
+		.type	__arm720_setup, #function
 __arm720_setup:	mov	r0, #0
 		mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
 		mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
@@ -143,6 +139,9 @@ __arm720_setup:	mov	r0, #0
 		orr	r0, r0, #0x2100			@ .... .... .111 .... (old)
 		orr	r0, r0, #0x003d			@ ..1. ..01 ..11 1101 (new)
 		mov	pc, lr				@ __ret (head-armv.S)
+		.size	__arm720_setup, . - __arm720_setup
+
+		__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -160,6 +159,8 @@ ENTRY(arm720_processor_functions)
 		.word	cpu_arm720_set_pte
 		.size	arm720_processor_functions, . - arm720_processor_functions
 
+		.section ".rodata"
+
 		.type	cpu_arch_name, #object
 cpu_arch_name:	.asciz	"armv4t"
 		.size	cpu_arch_name, . - cpu_arch_name
@@ -167,6 +168,12 @@ cpu_arch_name:	.asciz	"armv4t"
 		.type	cpu_elf_name, #object
 cpu_elf_name:	.asciz	"v4"
 		.size	cpu_elf_name, . - cpu_elf_name
+
+		.type	cpu_arm720_name, #object
+cpu_arm720_name:
+		.asciz	"ARM720T"
+		.size	cpu_arm720_name, . - cpu_arm720_name
+
 		.align
 
 /*

arch/arm/mm/proc-arm920.S

@@ -360,25 +360,9 @@ ENTRY(cpu_arm920_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm920_name)
-	.ascii	"ARM920T"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm920_setup, #function
 __arm920_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -409,8 +393,9 @@ __arm920_setup:
 	orr	r0, r0, #0x1000			@ ...1 .... .... ....
 #endif
 	mov	pc, lr
+	.size	__arm920_setup, . - __arm920_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -428,6 +413,8 @@ arm920_processor_functions:
 	.word	cpu_arm920_set_pte
 	.size	arm920_processor_functions, . - arm920_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4t"
@@ -437,6 +424,24 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm920_name, #object
+cpu_arm920_name:
+	.ascii	"ARM920T"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+	.size	cpu_arm920_name, . - cpu_arm920_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm922.S

@@ -364,25 +364,9 @@ ENTRY(cpu_arm922_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm922_name)
-	.ascii	"ARM922T"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm922_setup, #function
 __arm922_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -413,8 +397,9 @@ __arm922_setup:
 	orr	r0, r0, #0x1000			@ ...1 .... .... ....
 #endif
 	mov	pc, lr
+	.size	__arm922_setup, . - __arm922_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -432,6 +417,8 @@ arm922_processor_functions:
 	.word	cpu_arm922_set_pte
 	.size	arm922_processor_functions, . - arm922_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4t"
@@ -441,6 +428,24 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm922_name, #object
+cpu_arm922_name:
+	.ascii	"ARM922T"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+	.size	cpu_arm922_name, . - cpu_arm922_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm926.S

@@ -366,28 +366,9 @@ ENTRY(cpu_arm926_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm926_name)
-	.ascii	"ARM926EJ-S"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-	.ascii	"RR"
-#endif
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm926_setup, #function
 __arm926_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -428,8 +409,9 @@ __arm926_setup:
 	orr	r0, r0, #0x1000			@ ...1 .... .... ....
 #endif
 	mov	pc, lr
+	.size	__arm926_setup, . - __arm926_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -447,6 +429,8 @@ arm926_processor_functions:
 	.word	cpu_arm926_set_pte
 	.size	arm926_processor_functions, . - arm926_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5tej"
@@ -456,6 +440,27 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm926_name, #object
+cpu_arm926_name:
+	.ascii	"ARM926EJ-S"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+	.ascii	"RR"
+#endif
+#endif
+	.ascii	"\0"
+	.size	cpu_arm926_name, . - cpu_arm926_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-sa110.S

@@ -182,13 +182,9 @@ ENTRY(cpu_sa110_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-cpu_sa110_name:
-	.asciz	"StrongARM-110"
-	.align
-
 	__INIT
 
+	.type	__sa110_setup, #function
 __sa110_setup:
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
 	bic	r0, r0, #0x2e00			@ ..VI ZFRS BLDP WCAM
@@ -203,8 +199,9 @@ __sa110_setup:
 	mov	r10, #0x1f			@ Domains 0, 1 = client
 	mcr	p15, 0, r10, c3, c0		@ load domain access register
 	mov	pc, lr
+	.size	__sa110_setup, . - __sa110_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -218,16 +215,13 @@ ENTRY(sa110_processor_functions)
 	.word	cpu_sa110_proc_fin
 	.word	cpu_sa110_reset
 	.word	cpu_sa110_do_idle
-
-	/* dcache */
 	.word	cpu_sa110_dcache_clean_area
-
-	/* pgtable */
 	.word	cpu_sa110_switch_mm
 	.word	cpu_sa110_set_pte
-
 	.size	sa110_processor_functions, . - sa110_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4"
@@ -237,6 +231,12 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_sa110_name, #object
+cpu_sa110_name:
+	.asciz	"StrongARM-110"
+	.size	cpu_sa110_name, . - cpu_sa110_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-sa1100.S

@@ -206,15 +206,9 @@ ENTRY(cpu_sa1100_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-cpu_sa1100_name:
-	.asciz	"StrongARM-1100"
-cpu_sa1110_name:
-	.asciz	"StrongARM-1110"
-	.align
-
 	__INIT
 
+	.type	__sa1100_setup, #function
 __sa1100_setup:
 	mov	r10, #0
 	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
@@ -229,8 +223,9 @@ __sa1100_setup:
 	orr	r0, r0, #0x003d
 	orr	r0, r0, #0x3100			@ ..11 ...1 ..11 11.1
 	mov	pc, lr
+	.size	__sa1100_setup, . - __sa1100_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -252,6 +247,8 @@ ENTRY(sa1100_processor_functions)
 	.word	cpu_sa1100_set_pte
 	.size	sa1100_processor_functions, . - sa1100_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4"
@@ -261,6 +258,17 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_sa1100_name, #object
+cpu_sa1100_name:
+	.asciz	"StrongARM-1100"
+	.size	cpu_sa1100_name, . - cpu_sa1100_name
+
+	.type	cpu_sa1110_name, #object
+cpu_sa1110_name:
+	.asciz	"StrongARM-1110"
+	.size	cpu_sa1110_name, . - cpu_sa1110_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-xscale.S

@@ -571,22 +571,11 @@ ENTRY(cpu_xscale_set_pte)
 
 	.ltorg
 
-cpu_80200_name:
-	.asciz	"XScale-80200"
-
-cpu_80321_name:
-	.asciz	"XScale-IOP80321"
-
-cpu_pxa250_name:
-	.asciz	"XScale-PXA250"
-
-cpu_pxa210_name:
-	.asciz	"XScale-PXA210"
-
 	.align
 
 	__INIT
 
+	.type	__xscale_setup, #function
 __xscale_setup:
 	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
 	msr	cpsr_c, r0
@@ -605,8 +594,9 @@ __xscale_setup:
 	orr	r0, r0, #0x0005			@ .... .... .... .C.M
 	orr	r0, r0, #0x3900			@ ..VI Z..S .... ....
 	mov	pc, lr
+	.size	__xscale_setup, . - __xscale_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -625,6 +615,8 @@ ENTRY(xscale_processor_functions)
 	.word	cpu_xscale_set_pte
 	.size	xscale_processor_functions, . - xscale_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5te"
@@ -634,6 +626,27 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_80200_name, #object
+cpu_80200_name:
+	.asciz	"XScale-80200"
+	.size	cpu_80200_name, . - cpu_80200_name
+
+	.type	cpu_80321_name, #object
+cpu_80321_name:
+	.asciz	"XScale-IOP80321"
+	.size	cpu_80321_name, . - cpu_80321_name
+
+	.type	cpu_pxa250_name, #object
+cpu_pxa250_name:
+	.asciz	"XScale-PXA250"
+	.size	cpu_pxa250_name, . - cpu_pxa250_name
+
+	.type	cpu_pxa210_name, #object
+cpu_pxa210_name:
+	.asciz	"XScale-PXA210"
+	.size	cpu_pxa210_name, . - cpu_pxa210_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/tlb-v3.S

@@ -42,7 +42,7 @@ ENTRY(v3_flush_kern_tlb_range)
 	blo	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
 	.type	v3_tlb_fns, #object
 ENTRY(v3_tlb_fns)

arch/arm/mm/tlb-v4.S

@@ -55,7 +55,7 @@ ENTRY(v4_flush_user_tlb_range)
 .globl v4_flush_kern_tlb_range
 .equ v4_flush_kern_tlb_range, .v4_flush_kern_tlb_range
 
-	__INIT
+	__INITDATA
 
 	.type	v4_tlb_fns, #object
 ENTRY(v4_tlb_fns)

arch/arm/mm/tlb-v4wb.S

@@ -67,7 +67,7 @@ ENTRY(v4wb_flush_kern_tlb_range)
 	blo	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
 	.type	v4wb_tlb_fns, #object
 ENTRY(v4wb_tlb_fns)

arch/arm/mm/tlb-v4wbi.S

@@ -58,7 +58,7 @@ ENTRY(v4wbi_flush_kern_tlb_range)
 	blo	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
 	.type	v4wbi_tlb_fns, #object
 ENTRY(v4wbi_tlb_fns)