Commit c745884b authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

- fix and enable iceland/topaz support
- handle WC on platforms that don't support it

* 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: disable uvd and vce clockgating on Fiji
  drm/amdgpu: remove exp hardware support from iceland
  drm/amdgpu: load MEC ucode manually on iceland
  drm/amdgpu: don't load MEC2 on topaz
  drm/amdgpu: drop topaz support from gmc8 module
  drm/amdgpu: pull topaz gmc bits into gmc_v7
  drm/amdgpu: The VI specific EXE bit should only apply to GMC v8.0 above
  drm/amdgpu: iceland use CI based MC IP
  drm/amdgpu: move gmc7 support out of CIK dependency
  drm/amdgpu/gfx7: enable cp inst/reg error interrupts
  drm/amdgpu/gfx8: enable cp inst/reg error interrupts
  drm/amdgpu: mask out WC from BO on unsupported arches
  drm/radeon: mask out WC from BO on unsupported arches
  drm: add helper to check for wc memory support
  drm/amdgpu: no need to load MC firmware on fiji
parents ec71f128 6357b75a
...@@ -25,7 +25,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ ...@@ -25,7 +25,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
# add asic specific block # add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \ ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
amdgpu_amdkfd_gfx_v7.o amdgpu_amdkfd_gfx_v7.o
...@@ -34,6 +34,7 @@ amdgpu-y += \ ...@@ -34,6 +34,7 @@ amdgpu-y += \
# add GMC block # add GMC block
amdgpu-y += \ amdgpu-y += \
gmc_v7_0.o \
gmc_v8_0.o gmc_v8_0.o
# add IH block # add IH block
......
...@@ -256,11 +256,11 @@ static struct pci_device_id pciidlist[] = { ...@@ -256,11 +256,11 @@ static struct pci_device_id pciidlist[] = {
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
#endif #endif
/* topaz */ /* topaz */
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
/* tonga */ /* tonga */
{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <drm/drmP.h> #include <drm/drmP.h>
#include <drm/amdgpu_drm.h> #include <drm/amdgpu_drm.h>
#include <drm/drm_cache.h>
#include "amdgpu.h" #include "amdgpu.h"
#include "amdgpu_trace.h" #include "amdgpu_trace.h"
...@@ -261,6 +262,13 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, ...@@ -261,6 +262,13 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
AMDGPU_GEM_DOMAIN_OA); AMDGPU_GEM_DOMAIN_OA);
bo->flags = flags; bo->flags = flags;
/* For architectures that don't support WC memory,
* mask out the WC flag from the BO
*/
if (!drm_arch_can_wc_memory())
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
amdgpu_fill_placement_to_bo(bo, placement); amdgpu_fill_placement_to_bo(bo, placement);
/* Kernel allocation are uninterruptible */ /* Kernel allocation are uninterruptible */
r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
......
...@@ -808,7 +808,7 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, ...@@ -808,7 +808,7 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
flags |= AMDGPU_PTE_SNOOPED; flags |= AMDGPU_PTE_SNOOPED;
} }
if (adev->asic_type >= CHIP_TOPAZ) if (adev->asic_type >= CHIP_TONGA)
flags |= AMDGPU_PTE_EXECUTABLE; flags |= AMDGPU_PTE_EXECUTABLE;
flags |= AMDGPU_PTE_READABLE; flags |= AMDGPU_PTE_READABLE;
......
...@@ -4738,6 +4738,22 @@ static int gfx_v7_0_early_init(void *handle) ...@@ -4738,6 +4738,22 @@ static int gfx_v7_0_early_init(void *handle)
return 0; return 0;
} }
static int gfx_v7_0_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
if (r)
return r;
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
if (r)
return r;
return 0;
}
static int gfx_v7_0_sw_init(void *handle) static int gfx_v7_0_sw_init(void *handle)
{ {
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
...@@ -4890,6 +4906,8 @@ static int gfx_v7_0_hw_fini(void *handle) ...@@ -4890,6 +4906,8 @@ static int gfx_v7_0_hw_fini(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
gfx_v7_0_cp_enable(adev, false); gfx_v7_0_cp_enable(adev, false);
gfx_v7_0_rlc_stop(adev); gfx_v7_0_rlc_stop(adev);
gfx_v7_0_fini_pg(adev); gfx_v7_0_fini_pg(adev);
...@@ -5527,7 +5545,7 @@ static int gfx_v7_0_set_powergating_state(void *handle, ...@@ -5527,7 +5545,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
const struct amd_ip_funcs gfx_v7_0_ip_funcs = { const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
.early_init = gfx_v7_0_early_init, .early_init = gfx_v7_0_early_init,
.late_init = NULL, .late_init = gfx_v7_0_late_init,
.sw_init = gfx_v7_0_sw_init, .sw_init = gfx_v7_0_sw_init,
.sw_fini = gfx_v7_0_sw_fini, .sw_fini = gfx_v7_0_sw_fini,
.hw_init = gfx_v7_0_hw_init, .hw_init = gfx_v7_0_hw_init,
......
...@@ -111,7 +111,6 @@ MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); ...@@ -111,7 +111,6 @@ MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
MODULE_FIRMWARE("amdgpu/topaz_me.bin"); MODULE_FIRMWARE("amdgpu/topaz_me.bin");
MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
...@@ -828,7 +827,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) ...@@ -828,7 +827,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
if (adev->asic_type != CHIP_STONEY) { if ((adev->asic_type != CHIP_STONEY) &&
(adev->asic_type != CHIP_TOPAZ)) {
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
if (!err) { if (!err) {
...@@ -3851,10 +3851,16 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) ...@@ -3851,10 +3851,16 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
if (r) if (r)
return -EINVAL; return -EINVAL;
r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, if (adev->asic_type == CHIP_TOPAZ) {
AMDGPU_UCODE_ID_CP_MEC1); r = gfx_v8_0_cp_compute_load_microcode(adev);
if (r) if (r)
return -EINVAL; return r;
} else {
r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
AMDGPU_UCODE_ID_CP_MEC1);
if (r)
return -EINVAL;
}
} }
} }
...@@ -3901,6 +3907,8 @@ static int gfx_v8_0_hw_fini(void *handle) ...@@ -3901,6 +3907,8 @@ static int gfx_v8_0_hw_fini(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
gfx_v8_0_cp_enable(adev, false); gfx_v8_0_cp_enable(adev, false);
gfx_v8_0_rlc_stop(adev); gfx_v8_0_rlc_stop(adev);
gfx_v8_0_cp_compute_fini(adev); gfx_v8_0_cp_compute_fini(adev);
...@@ -4329,6 +4337,14 @@ static int gfx_v8_0_late_init(void *handle) ...@@ -4329,6 +4337,14 @@ static int gfx_v8_0_late_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r; int r;
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
if (r)
return r;
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
if (r)
return r;
/* requires IBs so do in late init after IB pool is initialized */ /* requires IBs so do in late init after IB pool is initialized */
r = gfx_v8_0_do_edc_gpr_workarounds(adev); r = gfx_v8_0_do_edc_gpr_workarounds(adev);
if (r) if (r)
......
...@@ -42,9 +42,39 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); ...@@ -42,9 +42,39 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
MODULE_FIRMWARE("radeon/bonaire_mc.bin"); MODULE_FIRMWARE("radeon/bonaire_mc.bin");
MODULE_FIRMWARE("radeon/hawaii_mc.bin"); MODULE_FIRMWARE("radeon/hawaii_mc.bin");
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
static const u32 golden_settings_iceland_a11[] =
{
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
};
static const u32 iceland_mgcg_cgcg_init[] =
{
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
};
static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev,
iceland_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_iceland_a11,
(const u32)ARRAY_SIZE(golden_settings_iceland_a11));
break;
default:
break;
}
}
/** /**
* gmc8_mc_wait_for_idle - wait for MC idle callback. * gmc7_mc_wait_for_idle - wait for MC idle callback.
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* *
...@@ -132,13 +162,20 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) ...@@ -132,13 +162,20 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
case CHIP_HAWAII: case CHIP_HAWAII:
chip_name = "hawaii"; chip_name = "hawaii";
break; break;
case CHIP_TOPAZ:
chip_name = "topaz";
break;
case CHIP_KAVERI: case CHIP_KAVERI:
case CHIP_KABINI: case CHIP_KABINI:
return 0; return 0;
default: BUG(); default: BUG();
} }
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); if (adev->asic_type == CHIP_TOPAZ)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
else
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
err = request_firmware(&adev->mc.fw, fw_name, adev->dev); err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
if (err) if (err)
goto out; goto out;
...@@ -984,6 +1021,8 @@ static int gmc_v7_0_hw_init(void *handle) ...@@ -984,6 +1021,8 @@ static int gmc_v7_0_hw_init(void *handle)
int r; int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gmc_v7_0_init_golden_registers(adev);
gmc_v7_0_mc_program(adev); gmc_v7_0_mc_program(adev);
if (!(adev->flags & AMD_IS_APU)) { if (!(adev->flags & AMD_IS_APU)) {
......
...@@ -42,9 +42,7 @@ ...@@ -42,9 +42,7 @@
static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
static const u32 golden_settings_tonga_a11[] = static const u32 golden_settings_tonga_a11[] =
{ {
...@@ -75,19 +73,6 @@ static const u32 fiji_mgcg_cgcg_init[] = ...@@ -75,19 +73,6 @@ static const u32 fiji_mgcg_cgcg_init[] =
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
}; };
static const u32 golden_settings_iceland_a11[] =
{
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
};
static const u32 iceland_mgcg_cgcg_init[] =
{
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
};
static const u32 cz_mgcg_cgcg_init[] = static const u32 cz_mgcg_cgcg_init[] =
{ {
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
...@@ -102,14 +87,6 @@ static const u32 stoney_mgcg_cgcg_init[] = ...@@ -102,14 +87,6 @@ static const u32 stoney_mgcg_cgcg_init[] =
static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev,
iceland_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_iceland_a11,
(const u32)ARRAY_SIZE(golden_settings_iceland_a11));
break;
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init, fiji_mgcg_cgcg_init,
...@@ -229,15 +206,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) ...@@ -229,15 +206,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n"); DRM_DEBUG("\n");
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ:
chip_name = "topaz";
break;
case CHIP_TONGA: case CHIP_TONGA:
chip_name = "tonga"; chip_name = "tonga";
break; break;
case CHIP_FIJI: case CHIP_FIJI:
chip_name = "fiji";
break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
case CHIP_STONEY: case CHIP_STONEY:
return 0; return 0;
...@@ -1007,7 +979,7 @@ static int gmc_v8_0_hw_init(void *handle) ...@@ -1007,7 +979,7 @@ static int gmc_v8_0_hw_init(void *handle)
gmc_v8_0_mc_program(adev); gmc_v8_0_mc_program(adev);
if (!(adev->flags & AMD_IS_APU)) { if (adev->asic_type == CHIP_TONGA) {
r = gmc_v8_0_mc_load_microcode(adev); r = gmc_v8_0_mc_load_microcode(adev);
if (r) { if (r) {
DRM_ERROR("Failed to load MC firmware!\n"); DRM_ERROR("Failed to load MC firmware!\n");
......
...@@ -432,7 +432,7 @@ static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type) ...@@ -432,7 +432,7 @@ static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type)
case AMDGPU_UCODE_ID_CP_ME: case AMDGPU_UCODE_ID_CP_ME:
return UCODE_ID_CP_ME_MASK; return UCODE_ID_CP_ME_MASK;
case AMDGPU_UCODE_ID_CP_MEC1: case AMDGPU_UCODE_ID_CP_MEC1:
return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK; return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
case AMDGPU_UCODE_ID_CP_MEC2: case AMDGPU_UCODE_ID_CP_MEC2:
return UCODE_ID_CP_MEC_MASK; return UCODE_ID_CP_MEC_MASK;
case AMDGPU_UCODE_ID_RLC_G: case AMDGPU_UCODE_ID_RLC_G:
...@@ -522,12 +522,6 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev) ...@@ -522,12 +522,6 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
return -EINVAL; return -EINVAL;
} }
if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
&toc->entry[toc->num_entries++])) {
DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
return -EINVAL;
}
if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0, if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
&toc->entry[toc->num_entries++])) { &toc->entry[toc->num_entries++])) {
DRM_ERROR("Failed to get firmware entry for SDMA0\n"); DRM_ERROR("Failed to get firmware entry for SDMA0\n");
...@@ -550,8 +544,8 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev) ...@@ -550,8 +544,8 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
UCODE_ID_CP_ME_MASK | UCODE_ID_CP_ME_MASK |
UCODE_ID_CP_PFP_MASK | UCODE_ID_CP_PFP_MASK |
UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_MASK |
UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT1_MASK;
UCODE_ID_CP_MEC_JT2_MASK;
if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) { if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
DRM_ERROR("Fail to request SMU load ucode\n"); DRM_ERROR("Fail to request SMU load ucode\n");
......
...@@ -61,6 +61,7 @@ ...@@ -61,6 +61,7 @@
#include "vi.h" #include "vi.h"
#include "vi_dpm.h" #include "vi_dpm.h"
#include "gmc_v8_0.h" #include "gmc_v8_0.h"
#include "gmc_v7_0.h"
#include "gfx_v8_0.h" #include "gfx_v8_0.h"
#include "sdma_v2_4.h" #include "sdma_v2_4.h"
#include "sdma_v3_0.h" #include "sdma_v3_0.h"
...@@ -1109,10 +1110,10 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] = ...@@ -1109,10 +1110,10 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
}, },
{ {
.type = AMD_IP_BLOCK_TYPE_GMC, .type = AMD_IP_BLOCK_TYPE_GMC,
.major = 8, .major = 7,
.minor = 0, .minor = 4,
.rev = 0, .rev = 0,
.funcs = &gmc_v8_0_ip_funcs, .funcs = &gmc_v7_0_ip_funcs,
}, },
{ {
.type = AMD_IP_BLOCK_TYPE_IH, .type = AMD_IP_BLOCK_TYPE_IH,
...@@ -1442,8 +1443,7 @@ static int vi_common_early_init(void *handle) ...@@ -1442,8 +1443,7 @@ static int vi_common_early_init(void *handle)
break; break;
case CHIP_FIJI: case CHIP_FIJI:
adev->has_uvd = true; adev->has_uvd = true;
adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG | adev->cg_flags = 0;
AMDGPU_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c; adev->external_rev_id = adev->rev_id + 0x3c;
break; break;
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <drm/drmP.h> #include <drm/drmP.h>
#include <drm/radeon_drm.h> #include <drm/radeon_drm.h>
#include <drm/drm_cache.h>
#include "radeon.h" #include "radeon.h"
#include "radeon_trace.h" #include "radeon_trace.h"
...@@ -245,6 +246,12 @@ int radeon_bo_create(struct radeon_device *rdev, ...@@ -245,6 +246,12 @@ int radeon_bo_create(struct radeon_device *rdev,
DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
"better performance thanks to write-combining\n"); "better performance thanks to write-combining\n");
bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
#else
/* For architectures that don't support WC memory,
* mask out the WC flag from the BO
*/
if (!drm_arch_can_wc_memory())
bo->flags &= ~RADEON_GEM_GTT_WC;
#endif #endif
radeon_ttm_placement_from_domain(bo, domain); radeon_ttm_placement_from_domain(bo, domain);
......
...@@ -35,4 +35,13 @@ ...@@ -35,4 +35,13 @@
void drm_clflush_pages(struct page *pages[], unsigned long num_pages); void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
static inline bool drm_arch_can_wc_memory(void)
{
#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
return false;
#else
return true;
#endif
}
#endif #endif
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