Commit c83e7d68 authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/gr/gm200: modify the mask when copying mmu settings from fb

Appears to more closely match what RM does.

For GM20B, now also copying bit 12 from NV_PFB_MMU_CTRL as upcoming
changes will require it.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 54aa38a8
...@@ -36,10 +36,8 @@ static void ...@@ -36,10 +36,8 @@ static void
gm200_gr_init_gpc_mmu(struct gf100_gr *gr) gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
{ {
struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_device *device = gr->base.engine.subdev.device;
u32 tmp;
tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */ nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff));
nvkm_wr32(device, 0x418890, 0x00000000); nvkm_wr32(device, 0x418890, 0x00000000);
nvkm_wr32(device, 0x418894, 0x00000000); nvkm_wr32(device, 0x418894, 0x00000000);
......
...@@ -42,7 +42,7 @@ gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) ...@@ -42,7 +42,7 @@ gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
} }
val = nvkm_rd32(device, 0x100c80); val = nvkm_rd32(device, 0x100c80);
val &= 0xf000087f; val &= 0xf000187f;
nvkm_wr32(device, 0x418880, val); nvkm_wr32(device, 0x418880, val);
nvkm_wr32(device, 0x418890, 0); nvkm_wr32(device, 0x418890, 0);
nvkm_wr32(device, 0x418894, 0); nvkm_wr32(device, 0x418894, 0);
......
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