Commit cad73da2 authored by Gregory Herrero's avatar Gregory Herrero Committed by Felipe Balbi

usb: dwc2: host: clear pending interrupts prior hibernation

If an interrupt rises during hibernation process, dwc2 will assert
interrupt line to interrupt controller. If interrupt is level
sensitive, interrupt handler will be called in a loop because dwc2
will not be able to clear it while controller is hibernated.
Thus, clear all controller interrupts before hibernation entry.
Signed-off-by: default avatarGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: default avatarMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: default avatarRobert Baldyga <r.baldyga@samsung.com>
Tested-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: default avatarJohn Youn <johnyoun@synopsys.com>
Acked-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 5bbf6ce0
......@@ -398,6 +398,12 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
}
}
/*
* Clear any pending interrupts since dwc2 will not be able to
* clear them after entering hibernation.
*/
dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
/* Put the controller in low power state */
pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment