Commit cad9b0af authored by Rajashekhara, Sudhakar's avatar Rajashekhara, Sudhakar Committed by Greg Kroah-Hartman

ASoC: davinci: fix codec start and stop functions

commit 3012f43e upstream.

According to DM365 voice codec data sheet at [1], before starting
recording or playback, ADC/DAC modules should follow a reset and
enable cycle. Writing a 1 to the ADC/DAC bit in the register resets
the module and clearing the bit to 0 will enable the module. But the
driver seems to be doing the reverse of it.

[1] http://focus.ti.com/lit/ug/sprufi9b/sprufi9b.pdfSigned-off-by: default avatarRajashekhara, Sudhakar <sudhakar.raj@ti.com>
Acked-by: default avatarLiam Girdwood <lrg@ti.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 6d1c18d3
...@@ -62,9 +62,9 @@ static void davinci_vcif_start(struct snd_pcm_substream *substream) ...@@ -62,9 +62,9 @@ static void davinci_vcif_start(struct snd_pcm_substream *substream)
w = readl(davinci_vc->base + DAVINCI_VC_CTRL); w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1); MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
else else
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1); MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
writel(w, davinci_vc->base + DAVINCI_VC_CTRL); writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
} }
...@@ -80,9 +80,9 @@ static void davinci_vcif_stop(struct snd_pcm_substream *substream) ...@@ -80,9 +80,9 @@ static void davinci_vcif_stop(struct snd_pcm_substream *substream)
/* Reset transmitter/receiver and sample rate/frame sync generators */ /* Reset transmitter/receiver and sample rate/frame sync generators */
w = readl(davinci_vc->base + DAVINCI_VC_CTRL); w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0); MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1);
else else
MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0); MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1);
writel(w, davinci_vc->base + DAVINCI_VC_CTRL); writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
} }
......
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