Commit cd07ecc8 authored by Tony Lindgren's avatar Tony Lindgren

Merge branch 'omap4' into for-next

parents 4c50d22a b04e8975
...@@ -127,6 +127,7 @@ endif ...@@ -127,6 +127,7 @@ endif
machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP1) := omap1
machine-$(CONFIG_ARCH_OMAP2) := omap2 machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2 machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
......
This diff is collapsed.
...@@ -25,7 +25,7 @@ config ARCH_OMAP3430 ...@@ -25,7 +25,7 @@ config ARCH_OMAP3430
select ARCH_OMAP_OTG select ARCH_OMAP_OTG
comment "OMAP Board Type" comment "OMAP Board Type"
depends on ARCH_OMAP2 || ARCH_OMAP3 depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
config MACH_OMAP_GENERIC config MACH_OMAP_GENERIC
bool "Generic OMAP board" bool "Generic OMAP board"
...@@ -75,3 +75,7 @@ config MACH_NOKIA_RX51 ...@@ -75,3 +75,7 @@ config MACH_NOKIA_RX51
config MACH_OMAP_ZOOM2 config MACH_OMAP_ZOOM2
bool "OMAP3 Zoom2 board" bool "OMAP3 Zoom2 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX depends on ARCH_OMAP3 && ARCH_OMAP34XX
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
depends on ARCH_OMAP4
...@@ -60,6 +60,9 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ ...@@ -60,6 +60,9 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \
mmc-twl4030.o \ mmc-twl4030.o \
board-zoom-debugboard.o board-zoom-debugboard.o
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
# Platform specific device init code # Platform specific device init code
obj-y += usb-musb.o obj-y += usb-musb.o
......
/*
* Board support file for OMAP4430 SDP.
*
* Copyright (C) 2009 Texas Instruments
*
* Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Based on mach-omap2/board-3430sdp.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/board.h>
#include <mach/common.h>
#include <mach/control.h>
#include <mach/timer-gp.h>
#include <asm/hardware/gic.h>
static struct platform_device sdp4430_lcd_device = {
.name = "sdp4430_lcd",
.id = -1,
};
static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_lcd_device,
};
static struct omap_uart_config sdp4430_uart_config __initdata = {
.enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2),
};
static struct omap_lcd_config sdp4430_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel sdp4430_config[] __initdata = {
{ OMAP_TAG_UART, &sdp4430_uart_config },
{ OMAP_TAG_LCD, &sdp4430_lcd_config },
};
static void __init gic_init_irq(void)
{
gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
}
static void __init omap_4430sdp_init_irq(void)
{
omap2_init_common_hw(NULL);
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1);
#endif
gic_init_irq();
omap_gpio_init();
}
static void __init omap_4430sdp_init(void)
{
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_board_config = sdp4430_config;
omap_board_config_size = ARRAY_SIZE(sdp4430_config);
omap_serial_init();
}
static void __init omap_4430sdp_map_io(void)
{
omap2_set_globals_443x();
omap2_map_common_io();
}
MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
/* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_4430sdp_map_io,
.init_irq = omap_4430sdp_init_irq,
.init_machine = omap_4430sdp_init,
.timer = &omap_timer,
MACHINE_END
...@@ -5,6 +5,9 @@ ...@@ -5,6 +5,9 @@
* *
* Author: Juha Yrjola * Author: Juha Yrjola
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
...@@ -424,6 +427,9 @@ void __init gpmc_init(void) ...@@ -424,6 +427,9 @@ void __init gpmc_init(void)
} else if (cpu_is_omap34xx()) { } else if (cpu_is_omap34xx()) {
ck = "gpmc_fck"; ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE; l = OMAP34XX_GPMC_BASE;
} else if (cpu_is_omap44xx()) {
ck = "gpmc_fck";
l = OMAP44XX_GPMC_BASE;
} }
gpmc_l3_clk = clk_get(NULL, ck); gpmc_l3_clk = clk_get(NULL, ck);
......
...@@ -6,6 +6,9 @@ ...@@ -6,6 +6,9 @@
* Copyright (C) 2005 Nokia Corporation * Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com> * Written by Tony Lindgren <tony@atomide.com>
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
...@@ -200,7 +203,10 @@ void __init omap2_check_revision(void) ...@@ -200,7 +203,10 @@ void __init omap2_check_revision(void)
omap24xx_check_revision(); omap24xx_check_revision();
else if (cpu_is_omap34xx()) else if (cpu_is_omap34xx())
omap34xx_check_revision(); omap34xx_check_revision();
else else if (cpu_is_omap44xx()) {
printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
return;
} else
pr_err("OMAP revision unknown, please fix!\n"); pr_err("OMAP revision unknown, please fix!\n");
/* /*
......
...@@ -4,12 +4,14 @@ ...@@ -4,12 +4,14 @@
* OMAP2 I/O mapping code * OMAP2 I/O mapping code
* *
* Copyright (C) 2005 Nokia Corporation * Copyright (C) 2005 Nokia Corporation
* Copyright (C) 2007 Texas Instruments * Copyright (C) 2007-2009 Texas Instruments
* *
* Author: * Author:
* Juha Yrjola <juha.yrjola@nokia.com> * Juha Yrjola <juha.yrjola@nokia.com>
* Syed Khasim <x0khasim@ti.com> * Syed Khasim <x0khasim@ti.com>
* *
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
...@@ -30,6 +32,7 @@ ...@@ -30,6 +32,7 @@
#include <mach/sdrc.h> #include <mach/sdrc.h>
#include <mach/gpmc.h> #include <mach/gpmc.h>
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
#include "clock.h" #include "clock.h"
#include <mach/powerdomain.h> #include <mach/powerdomain.h>
...@@ -38,7 +41,7 @@ ...@@ -38,7 +41,7 @@
#include <mach/clockdomain.h> #include <mach/clockdomain.h>
#include "clockdomains.h" #include "clockdomains.h"
#endif
/* /*
* The machine specific code may provide the extra mapping besides the * The machine specific code may provide the extra mapping besides the
* default mapping provided here. * default mapping provided here.
...@@ -166,6 +169,46 @@ static struct map_desc omap34xx_io_desc[] __initdata = { ...@@ -166,6 +169,46 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
}, },
}; };
#endif #endif
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
.virtual = L3_44XX_VIRT,
.pfn = __phys_to_pfn(L3_44XX_PHYS),
.length = L3_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_44XX_VIRT,
.pfn = __phys_to_pfn(L4_44XX_PHYS),
.length = L4_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_WK_44XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
.length = L4_WK_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = OMAP44XX_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
.length = OMAP44XX_GPMC_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER_44XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
.length = L4_PER_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_EMU_44XX_VIRT,
.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
.length = L4_EMU_44XX_SIZE,
.type = MT_DEVICE,
},
};
#endif
void __init omap2_map_common_io(void) void __init omap2_map_common_io(void)
{ {
...@@ -183,6 +226,9 @@ void __init omap2_map_common_io(void) ...@@ -183,6 +226,9 @@ void __init omap2_map_common_io(void)
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
#endif #endif
#if defined(CONFIG_ARCH_OMAP4)
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
#endif
/* Normally devicemaps_init() would flush caches and tlb after /* Normally devicemaps_init() would flush caches and tlb after
* mdesc->map_io(), but we must also do it here because of the CPU * mdesc->map_io(), but we must also do it here because of the CPU
* revision check below. * revision check below.
...@@ -198,9 +244,11 @@ void __init omap2_map_common_io(void) ...@@ -198,9 +244,11 @@ void __init omap2_map_common_io(void)
void __init omap2_init_common_hw(struct omap_sdrc_params *sp) void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
{ {
omap2_mux_init(); omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
pwrdm_init(powerdomains_omap); pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init(); omap2_clk_init();
omap2_sdrc_init(sp); omap2_sdrc_init(sp);
#endif
gpmc_init(); gpmc_init();
} }
...@@ -10,6 +10,9 @@ ...@@ -10,6 +10,9 @@
* *
* Based off of arch/arm/mach-omap/omap1/serial.c * Based off of arch/arm/mach-omap/omap1/serial.c
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
*
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
...@@ -493,6 +496,10 @@ void __init omap_serial_init(void) ...@@ -493,6 +496,10 @@ void __init omap_serial_init(void)
if (info == NULL) if (info == NULL)
return; return;
if (cpu_is_omap44xx()) {
for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
serial_platform_data[i].irq += 32;
}
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
struct plat_serial8250_port *p = serial_platform_data + i; struct plat_serial8250_port *p = serial_platform_data + i;
......
...@@ -17,9 +17,10 @@ ...@@ -17,9 +17,10 @@
* *
* Some parts based off of TI's 24xx code: * Some parts based off of TI's 24xx code:
* *
* Copyright (C) 2004 Texas Instruments, Inc. * Copyright (C) 2004-2009 Texas Instruments, Inc.
* *
* Roughly modelled after the OMAP1 MPU timer code. * Roughly modelled after the OMAP1 MPU timer code.
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
* *
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
...@@ -82,7 +83,8 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, ...@@ -82,7 +83,8 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
case CLOCK_EVT_MODE_PERIODIC: case CLOCK_EVT_MODE_PERIODIC:
period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
period -= 1; period -= 1;
if (cpu_is_omap44xx())
period = 0xff; /* FIXME: */
omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
break; break;
case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_ONESHOT:
...@@ -145,6 +147,9 @@ static void __init omap2_gp_clockevent_init(void) ...@@ -145,6 +147,9 @@ static void __init omap2_gp_clockevent_init(void)
"timer-gp: omap_dm_timer_set_source() failed\n"); "timer-gp: omap_dm_timer_set_source() failed\n");
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
if (cpu_is_omap44xx())
/* Assuming 32kHz clk is driving GPT1 */
tick_rate = 32768; /* FIXME: */
pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
gptimer_id, tick_rate); gptimer_id, tick_rate);
......
...@@ -23,6 +23,11 @@ config ARCH_OMAP3 ...@@ -23,6 +23,11 @@ config ARCH_OMAP3
select CPU_V7 select CPU_V7
select COMMON_CLKDEV select COMMON_CLKDEV
config ARCH_OMAP4
bool "TI OMAP4"
select CPU_V7
select ARM_GIC
endchoice endchoice
comment "OMAP Feature Selections" comment "OMAP Feature Selections"
...@@ -128,13 +133,13 @@ config OMAP_MPU_TIMER ...@@ -128,13 +133,13 @@ config OMAP_MPU_TIMER
config OMAP_32K_TIMER config OMAP_32K_TIMER
bool "Use 32KHz timer" bool "Use 32KHz timer"
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
help help
Select this option if you want to enable the OMAP 32KHz timer. Select this option if you want to enable the OMAP 32KHz timer.
This timer saves power compared to the OMAP_MPU_TIMER, and has This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
currently only available for OMAP16XX, 24XX and 34XX. currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
endchoice endchoice
...@@ -149,7 +154,7 @@ config OMAP_32K_TIMER_HZ ...@@ -149,7 +154,7 @@ config OMAP_32K_TIMER_HZ
config OMAP_DM_TIMER config OMAP_DM_TIMER
bool "Use dual-mode timer" bool "Use dual-mode timer"
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
help help
Select this option if you want to use OMAP Dual-Mode timers. Select this option if you want to use OMAP Dual-Mode timers.
......
...@@ -36,10 +36,40 @@ static struct clk_functions *arch_clock; ...@@ -36,10 +36,40 @@ static struct clk_functions *arch_clock;
* Standard clock functions defined in include/linux/clk.h * Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
/* This functions is moved to arch/arm/common/clkdev.c. For OMAP4 since
* clock framework is not up , it is defined here to avoid rework in
* every driver. Also dummy prcm reset function is added */
/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */
#if defined(CONFIG_ARCH_OMAP4)
struct clk *clk_get(struct device *dev, const char *id)
{
return NULL;
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
void omap2_clk_prepare_for_reboot(void)
{
}
EXPORT_SYMBOL(omap2_clk_prepare_for_reboot);
void omap_prcm_arch_reset(char mode)
{
}
EXPORT_SYMBOL(omap_prcm_arch_reset);
#endif
int clk_enable(struct clk *clk) int clk_enable(struct clk *clk)
{ {
unsigned long flags; unsigned long flags;
int ret = 0; int ret = 0;
if (cpu_is_omap44xx())
/* OMAP4 clk framework not supported yet */
return 0;
if (clk == NULL || IS_ERR(clk)) if (clk == NULL || IS_ERR(clk))
return -EINVAL; return -EINVAL;
...@@ -140,6 +170,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent) ...@@ -140,6 +170,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
unsigned long flags; unsigned long flags;
int ret = -EINVAL; int ret = -EINVAL;
if (cpu_is_omap44xx())
/* OMAP4 clk framework not supported yet */
return 0;
if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
return ret; return ret;
......
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
* linux/arch/arm/plat-omap/common.c * linux/arch/arm/plat-omap/common.c
* *
* Code common to all OMAP machines. * Code common to all OMAP machines.
* The file is created by Tony Lindgren <tony@atomide.com>
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -216,6 +220,15 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs) ...@@ -216,6 +220,15 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs)
#define omap34xx_32k_read NULL #define omap34xx_32k_read NULL
#endif #endif
#ifdef CONFIG_ARCH_OMAP4
static cycle_t omap44xx_32k_read(struct clocksource *cs)
{
return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10);
}
#else
#define omap44xx_32k_read NULL
#endif
/* /*
* Kernel assumes that sched_clock can be called early but may not have * Kernel assumes that sched_clock can be called early but may not have
* things ready yet. * things ready yet.
...@@ -263,6 +276,8 @@ static int __init omap_init_clocksource_32k(void) ...@@ -263,6 +276,8 @@ static int __init omap_init_clocksource_32k(void)
clocksource_32k.read = omap2430_32k_read; clocksource_32k.read = omap2430_32k_read;
else if (cpu_is_omap34xx()) else if (cpu_is_omap34xx())
clocksource_32k.read = omap34xx_32k_read; clocksource_32k.read = omap34xx_32k_read;
else if (cpu_is_omap44xx())
clocksource_32k.read = omap44xx_32k_read;
else else
return -ENODEV; return -ENODEV;
...@@ -350,3 +365,19 @@ void __init omap2_set_globals_343x(void) ...@@ -350,3 +365,19 @@ void __init omap2_set_globals_343x(void)
} }
#endif #endif
#if defined(CONFIG_ARCH_OMAP4)
static struct omap_globals omap4_globals = {
.class = OMAP443X_CLASS,
.tap = OMAP2_IO_ADDRESS(0x4830a000),
.ctrl = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE),
.prm = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE),
.cm = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE),
};
void __init omap2_set_globals_443x(void)
{
omap2_set_globals_tap(&omap4_globals);
omap2_set_globals_control(&omap4_globals);
}
#endif
...@@ -311,6 +311,8 @@ static void omap_init_wdt(void) ...@@ -311,6 +311,8 @@ static void omap_init_wdt(void)
wdt_resources[0].start = 0x49016000; /* WDT2 */ wdt_resources[0].start = 0x49016000; /* WDT2 */
else if (cpu_is_omap343x()) else if (cpu_is_omap343x())
wdt_resources[0].start = 0x48314000; /* WDT2 */ wdt_resources[0].start = 0x48314000; /* WDT2 */
else if (cpu_is_omap44xx())
wdt_resources[0].start = 0x4a314000;
else else
return; return;
......
...@@ -10,6 +10,9 @@ ...@@ -10,6 +10,9 @@
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Support functions for the OMAP internal DMA channels. * Support functions for the OMAP internal DMA channels.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
...@@ -872,7 +875,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, ...@@ -872,7 +875,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
} }
l = dma_read(CCR(lch)); l = dma_read(CCR(lch));
l &= ~((1 << 6) | (1 << 26)); l &= ~((1 << 6) | (1 << 26));
if (cpu_is_omap2430() || cpu_is_omap34xx()) if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
else else
l |= ((read_prio & 0x1) << 6); l |= ((read_prio & 0x1) << 6);
...@@ -1844,7 +1847,8 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) ...@@ -1844,7 +1847,8 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
#define omap1_dma_irq_handler NULL #define omap1_dma_irq_handler NULL
#endif #endif
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
static int omap2_dma_handle_ch(int ch) static int omap2_dma_handle_ch(int ch)
{ {
...@@ -2339,6 +2343,9 @@ static int __init omap_init_dma(void) ...@@ -2339,6 +2343,9 @@ static int __init omap_init_dma(void)
} else if (cpu_is_omap34xx()) { } else if (cpu_is_omap34xx()) {
omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE); omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap44xx()) {
omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else { } else {
pr_err("DMA init failed for unsupported omap\n"); pr_err("DMA init failed for unsupported omap\n");
return -ENODEV; return -ENODEV;
...@@ -2437,12 +2444,18 @@ static int __init omap_init_dma(void) ...@@ -2437,12 +2444,18 @@ static int __init omap_init_dma(void)
} }
} }
if (cpu_is_omap2430() || cpu_is_omap34xx()) if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
DMA_DEFAULT_FIFO_DEPTH, 0); DMA_DEFAULT_FIFO_DEPTH, 0);
if (cpu_class_is_omap2()) if (cpu_class_is_omap2()) {
setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq); int irq;
if (cpu_is_omap44xx())
irq = INT_44XX_SDMA_IRQ0;
else
irq = INT_24XX_SDMA_IRQ0;
setup_irq(irq, &omap24xx_dma_irq);
}
/* FIXME: Update LCD DMA to work on 24xx */ /* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) { if (cpu_class_is_omap1()) {
......
...@@ -7,6 +7,9 @@ ...@@ -7,6 +7,9 @@
* OMAP2 support by Juha Yrjola * OMAP2 support by Juha Yrjola
* API improvements and OMAP2 clock framework support by Timo Teras * API improvements and OMAP2 clock framework support by Timo Teras
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your * Free Software Foundation; either version 2 of the License, or (at your
...@@ -150,7 +153,8 @@ ...@@ -150,7 +153,8 @@
struct omap_dm_timer { struct omap_dm_timer {
unsigned long phys_base; unsigned long phys_base;
int irq; int irq;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
struct clk *iclk, *fclk; struct clk *iclk, *fclk;
#endif #endif
void __iomem *io_base; void __iomem *io_base;
...@@ -169,6 +173,9 @@ struct omap_dm_timer { ...@@ -169,6 +173,9 @@ struct omap_dm_timer {
#define omap3_dm_timers NULL #define omap3_dm_timers NULL
#define omap3_dm_source_names NULL #define omap3_dm_source_names NULL
#define omap3_dm_source_clocks NULL #define omap3_dm_source_clocks NULL
#define omap4_dm_timers NULL
#define omap4_dm_source_names NULL
#define omap4_dm_source_clocks NULL
static struct omap_dm_timer omap1_dm_timers[] = { static struct omap_dm_timer omap1_dm_timers[] = {
{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
...@@ -191,6 +198,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); ...@@ -191,6 +198,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
#define omap3_dm_timers NULL #define omap3_dm_timers NULL
#define omap3_dm_source_names NULL #define omap3_dm_source_names NULL
#define omap3_dm_source_clocks NULL #define omap3_dm_source_clocks NULL
#define omap4_dm_timers NULL
#define omap4_dm_source_names NULL
#define omap4_dm_source_clocks NULL
static struct omap_dm_timer omap2_dm_timers[] = { static struct omap_dm_timer omap2_dm_timers[] = {
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
...@@ -225,6 +235,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); ...@@ -225,6 +235,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
#define omap2_dm_timers NULL #define omap2_dm_timers NULL
#define omap2_dm_source_names NULL #define omap2_dm_source_names NULL
#define omap2_dm_source_clocks NULL #define omap2_dm_source_clocks NULL
#define omap4_dm_timers NULL
#define omap4_dm_source_names NULL
#define omap4_dm_source_clocks NULL
static struct omap_dm_timer omap3_dm_timers[] = { static struct omap_dm_timer omap3_dm_timers[] = {
{ .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
...@@ -250,6 +263,40 @@ static const char *omap3_dm_source_names[] __initdata = { ...@@ -250,6 +263,40 @@ static const char *omap3_dm_source_names[] __initdata = {
static struct clk *omap3_dm_source_clocks[2]; static struct clk *omap3_dm_source_clocks[2];
static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
#elif defined(CONFIG_ARCH_OMAP4)
#define omap_dm_clk_enable(x) clk_enable(x)
#define omap_dm_clk_disable(x) clk_disable(x)
#define omap1_dm_timers NULL
#define omap2_dm_timers NULL
#define omap2_dm_source_names NULL
#define omap2_dm_source_clocks NULL
#define omap3_dm_timers NULL
#define omap3_dm_source_names NULL
#define omap3_dm_source_clocks NULL
static struct omap_dm_timer omap4_dm_timers[] = {
{ .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
{ .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
{ .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 },
{ .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 },
{ .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 },
{ .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 },
{ .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 },
{ .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 },
{ .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 },
{ .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 },
{ .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 },
{ .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 },
};
static const char *omap4_dm_source_names[] __initdata = {
"sys_ck",
"omap_32k_fck",
NULL
};
static struct clk *omap4_dm_source_clocks[2];
static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
#else #else
#error OMAP architecture not supported! #error OMAP architecture not supported!
...@@ -459,7 +506,8 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) ...@@ -459,7 +506,8 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
} }
EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) #elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{ {
...@@ -711,6 +759,10 @@ int __init omap_dm_timer_init(void) ...@@ -711,6 +759,10 @@ int __init omap_dm_timer_init(void)
dm_timers = omap3_dm_timers; dm_timers = omap3_dm_timers;
dm_source_names = omap3_dm_source_names; dm_source_names = omap3_dm_source_names;
dm_source_clocks = omap3_dm_source_clocks; dm_source_clocks = omap3_dm_source_clocks;
} else if (cpu_is_omap44xx()) {
dm_timers = omap4_dm_timers;
dm_source_names = omap4_dm_source_names;
dm_source_clocks = omap4_dm_source_clocks;
} }
if (cpu_class_is_omap2()) if (cpu_class_is_omap2())
...@@ -723,7 +775,8 @@ int __init omap_dm_timer_init(void) ...@@ -723,7 +775,8 @@ int __init omap_dm_timer_init(void)
for (i = 0; i < dm_timer_count; i++) { for (i = 0; i < dm_timer_count; i++) {
timer = &dm_timers[i]; timer = &dm_timers[i];
timer->io_base = IO_ADDRESS(timer->phys_base); timer->io_base = IO_ADDRESS(timer->phys_base);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
if (cpu_class_is_omap2()) { if (cpu_class_is_omap2()) {
char clk_name[16]; char clk_name[16];
sprintf(clk_name, "gpt%d_ick", i + 1); sprintf(clk_name, "gpt%d_ick", i + 1);
......
This diff is collapsed.
...@@ -22,7 +22,8 @@ struct clkops { ...@@ -22,7 +22,8 @@ struct clkops {
void (*disable)(struct clk *); void (*disable)(struct clk *);
}; };
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
struct clksel_rate { struct clksel_rate {
u32 val; u32 val;
...@@ -51,7 +52,7 @@ struct dpll_data { ...@@ -51,7 +52,7 @@ struct dpll_data {
u8 max_divider; u8 max_divider;
u32 max_tolerance; u32 max_tolerance;
u16 max_multiplier; u16 max_multiplier;
# if defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
u8 modes; u8 modes;
void __iomem *autoidle_reg; void __iomem *autoidle_reg;
void __iomem *idlest_reg; void __iomem *idlest_reg;
...@@ -83,7 +84,8 @@ struct clk { ...@@ -83,7 +84,8 @@ struct clk {
void (*init)(struct clk *); void (*init)(struct clk *);
__u8 enable_bit; __u8 enable_bit;
__s8 usecount; __s8 usecount;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
u8 fixed_div; u8 fixed_div;
void __iomem *clksel_reg; void __iomem *clksel_reg;
u32 clksel_mask; u32 clksel_mask;
......
...@@ -60,6 +60,7 @@ struct omap_globals { ...@@ -60,6 +60,7 @@ struct omap_globals {
void omap2_set_globals_242x(void); void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void); void omap2_set_globals_243x(void);
void omap2_set_globals_343x(void); void omap2_set_globals_343x(void);
void omap2_set_globals_443x(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */ /* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_tap(struct omap_globals *);
......
/* /*
* arch/arm/plat-omap/include/mach/control.h * arch/arm/plat-omap/include/mach/control.h
* *
* OMAP2/3 System Control Module definitions * OMAP2/3/4 System Control Module definitions
* *
* Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation * Copyright (C) 2007-2008 Nokia Corporation
* *
* Written by Paul Walmsley * Written by Paul Walmsley
...@@ -203,7 +203,8 @@ ...@@ -203,7 +203,8 @@
#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
extern void __iomem *omap_ctrl_base_get(void); extern void __iomem *omap_ctrl_base_get(void);
extern u8 omap_ctrl_readb(u16 offset); extern u8 omap_ctrl_readb(u16 offset);
extern u16 omap_ctrl_readw(u16 offset); extern u16 omap_ctrl_readw(u16 offset);
......
...@@ -5,8 +5,12 @@ ...@@ -5,8 +5,12 @@
* *
* Copyright (C) 2004, 2008 Nokia Corporation * Copyright (C) 2004, 2008 Nokia Corporation
* *
* Copyright (C) 2009 Texas Instruments.
*
* Written by Tony Lindgren <tony.lindgren@nokia.com> * Written by Tony Lindgren <tony.lindgren@nokia.com>
* *
* Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
...@@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343) ...@@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
#define cpu_is_omap243x() 0 #define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0 #define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0 #define cpu_is_omap343x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
#if defined(MULTI_OMAP1) #if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730) # if defined(CONFIG_ARCH_OMAP730)
...@@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430) ...@@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430)
# define cpu_is_omap3430() is_omap3430() # define cpu_is_omap3430() is_omap3430()
#endif #endif
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
# define cpu_is_omap44xx() 1
# define cpu_is_omap443x() 1
# endif
/* Macros to detect if we have OMAP1 or OMAP2 */ /* Macros to detect if we have OMAP1 or OMAP2 */
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
cpu_is_omap16xx()) cpu_is_omap16xx())
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
cpu_is_omap44xx())
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
/* Various silicon revisions for omap2 */ /* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024 #define OMAP242X_CLASS 0x24200024
...@@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430) ...@@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP3430_REV_ES3_0 0x34303034 #define OMAP3430_REV_ES3_0 0x34303034
#define OMAP3430_REV_ES3_1 0x34304034 #define OMAP3430_REV_ES3_1 0x34304034
#define OMAP443X_CLASS 0x44300034
/* /*
* omap_chip bits * omap_chip bits
* *
......
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
add \rx, \rx, #0x00004000 @ UART 3 add \rx, \rx, #0x00004000 @ UART 3
#endif #endif
#elif CONFIG_ARCH_OMAP3 #elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
moveq \rx, #0x48000000 @ physical base address moveq \rx, #0x48000000 @ physical base address
movne \rx, #0xd8000000 @ virtual base movne \rx, #0xd8000000 @ virtual base
orr \rx, \rx, #0x0006a000 orr \rx, \rx, #0x0006a000
......
...@@ -48,6 +48,7 @@ ...@@ -48,6 +48,7 @@
/* Hardware registers for omap2 and omap3 */ /* Hardware registers for omap2 and omap3 */
#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
#define OMAP_DMA4_REVISION 0x00 #define OMAP_DMA4_REVISION 0x00
#define OMAP_DMA4_GCR 0x78 #define OMAP_DMA4_GCR 0x78
......
...@@ -3,6 +3,9 @@ ...@@ -3,6 +3,9 @@
* *
* Low-level IRQ helper macros for OMAP-based platforms * Low-level IRQ helper macros for OMAP-based platforms
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
...@@ -10,6 +13,7 @@ ...@@ -10,6 +13,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/io.h> #include <mach/io.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#include <asm/hardware/gic.h>
#if defined(CONFIG_ARCH_OMAP1) #if defined(CONFIG_ARCH_OMAP1)
...@@ -56,7 +60,8 @@ ...@@ -56,7 +60,8 @@
.endm .endm
#endif #endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
defined(CONFIG_ARCH_OMAP4)
#include <mach/omap24xx.h> #include <mach/omap24xx.h>
#include <mach/omap34xx.h> #include <mach/omap34xx.h>
...@@ -67,7 +72,9 @@ ...@@ -67,7 +72,9 @@
#elif defined(CONFIG_ARCH_OMAP34XX) #elif defined(CONFIG_ARCH_OMAP34XX)
#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
#endif #endif
#if defined(CONFIG_ARCH_OMAP4)
#include <mach/omap44xx.h>
#endif
#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
...@@ -80,6 +87,7 @@ ...@@ -80,6 +87,7 @@
.macro arch_ret_to_user, tmp1, tmp2 .macro arch_ret_to_user, tmp1, tmp2
.endm .endm
#ifndef CONFIG_ARCH_OMAP4
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =OMAP2_VA_IC_BASE ldr \base, =OMAP2_VA_IC_BASE
ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
...@@ -95,6 +103,40 @@ ...@@ -95,6 +103,40 @@
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
.endm .endm
#else
/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Interrupts 0-15 are IPI
* 16-28 are reserved
* 29-31 are local. We allow 30 to be used for the watchdog.
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* For now, we ignore all local interrupts so only return an
* interrupt if it's between 30 and 1020. The test_for_ipi
* routine below will pick up on IPIs.
* A simple read from the controller will tell us the number
* of the highest priority enabled interrupt.
* We then just need to check whether it is in the
* valid range for an IRQ (30-1020 inclusive).
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
ldr \irqstat, [\base, #GIC_CPU_INTACK]
ldr \tmp, =1021
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #29
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
#endif
.macro irq_prio_table .macro irq_prio_table
.endm .endm
......
...@@ -285,5 +285,6 @@ ...@@ -285,5 +285,6 @@
#include "omap16xx.h" #include "omap16xx.h"
#include "omap24xx.h" #include "omap24xx.h"
#include "omap34xx.h" #include "omap34xx.h"
#include "omap44xx.h"
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */
...@@ -6,6 +6,9 @@ ...@@ -6,6 +6,9 @@
* Copied from arch/arm/mach-sa1100/include/mach/io.h * Copied from arch/arm/mach-sa1100/include/mach/io.h
* Copyright (C) 1997-1999 Russell King * Copyright (C) 1997-1999 Russell King
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your * Free Software Foundation; either version 2 of the License, or (at your
...@@ -157,6 +160,40 @@ ...@@ -157,6 +160,40 @@
#define DSP_MMU_34XX_VIRT 0xe2000000 #define DSP_MMU_34XX_VIRT 0xe2000000
#define DSP_MMU_34XX_SIZE SZ_4K #define DSP_MMU_34XX_SIZE SZ_4K
#elif defined(CONFIG_ARCH_OMAP4)
/* We map both L3 and L4 on OMAP4 */
#define L3_44XX_PHYS L3_44XX_BASE
#define L3_44XX_VIRT 0xd4000000
#define L3_44XX_SIZE SZ_1M
#define L4_44XX_PHYS L4_44XX_BASE
#define L4_44XX_VIRT 0xda000000
#define L4_44XX_SIZE SZ_4M
#define L4_WK_44XX_PHYS L4_WK_44XX_BASE
#define L4_WK_44XX_VIRT 0xda300000
#define L4_WK_44XX_SIZE SZ_1M
#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
#define L4_PER_44XX_VIRT 0xd8000000
#define L4_PER_44XX_SIZE SZ_4M
#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
#define L4_EMU_44XX_VIRT 0xe4000000
#define L4_EMU_44XX_SIZE SZ_64M
#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
#define OMAP44XX_GPMC_VIRT 0xe0000000
#define OMAP44XX_GPMC_SIZE SZ_1M
#define IO_OFFSET 0x90000000
#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
#endif #endif
#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
......
...@@ -4,6 +4,9 @@ ...@@ -4,6 +4,9 @@
* Copyright (C) Greg Lonnon 2001 * Copyright (C) Greg Lonnon 2001
* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
...@@ -422,6 +425,92 @@ ...@@ -422,6 +425,92 @@
#define INT_34XX_BENCH_MPU_EMUL 3 #define INT_34XX_BENCH_MPU_EMUL 3
#define IRQ_GIC_START 32
#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
* 16 MPUIO lines */ * 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192 #define OMAP_MAX_GPIO_LINES 192
......
...@@ -38,7 +38,8 @@ ...@@ -38,7 +38,8 @@
*/ */
#if defined(CONFIG_ARCH_OMAP1) #if defined(CONFIG_ARCH_OMAP1)
#define PHYS_OFFSET UL(0x10000000) #define PHYS_OFFSET UL(0x10000000)
#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) #elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
#define PHYS_OFFSET UL(0x80000000) #define PHYS_OFFSET UL(0x80000000)
#endif #endif
......
/*:
* Address mappings and base address for OMAP4 interconnects
* and peripherals.
*
* Copyright (C) 2009 Texas Instruments
*
* Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_OMAP44XX_H
#define __ASM_ARCH_OMAP44XX_H
/*
* Please place only base defines here and put the rest in device
* specific headers.
*/
#define L4_44XX_BASE 0x4a000000
#define L4_WK_44XX_BASE 0x4a300000
#define L4_PER_44XX_BASE 0x48000000
#define L4_EMU_44XX_BASE 0x54000000
#define L3_44XX_BASE 0x44000000
#define OMAP4430_32KSYNCT_BASE 0x4a304000
#define OMAP4430_CM_BASE 0x4a004000
#define OMAP4430_PRM_BASE 0x48306000
#define OMAP44XX_GPMC_BASE 0x50000000
#define OMAP443X_SCM_BASE 0x4a002000
#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
#define OMAP44XX_IC_BASE 0x48200000
#define OMAP44XX_IVA_INTC_BASE 0x40000000
#define IRQ_SIR_IRQ 0x0040
#define OMAP44XX_GIC_DIST_BASE 0x48241000
#define OMAP44XX_GIC_CPU_BASE 0x48240100
#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
#define OMAP44XX_SCU_BASE 0x48240000
#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE)
#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
#define OMAP44XX_WKUPGEN_BASE 0x48281000
#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
#endif /* __ASM_ARCH_OMAP44XX_H */
/* /*
* arch/arm/plat-omap/include/mach/serial.h * arch/arm/plat-omap/include/mach/serial.h
*
* Copyright (C) 2009 Texas Instruments
* Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
...@@ -15,19 +18,28 @@ ...@@ -15,19 +18,28 @@
#define OMAP_UART1_BASE 0xfffb0000 #define OMAP_UART1_BASE 0xfffb0000
#define OMAP_UART2_BASE 0xfffb0800 #define OMAP_UART2_BASE 0xfffb0800
#define OMAP_UART3_BASE 0xfffb9800 #define OMAP_UART3_BASE 0xfffb9800
#define OMAP_MAX_NR_PORTS 3
#elif defined(CONFIG_ARCH_OMAP2) #elif defined(CONFIG_ARCH_OMAP2)
/* OMAP2 serial ports */ /* OMAP2 serial ports */
#define OMAP_UART1_BASE 0x4806a000 #define OMAP_UART1_BASE 0x4806a000
#define OMAP_UART2_BASE 0x4806c000 #define OMAP_UART2_BASE 0x4806c000
#define OMAP_UART3_BASE 0x4806e000 #define OMAP_UART3_BASE 0x4806e000
#define OMAP_MAX_NR_PORTS 3
#elif defined(CONFIG_ARCH_OMAP3) #elif defined(CONFIG_ARCH_OMAP3)
/* OMAP3 serial ports */ /* OMAP3 serial ports */
#define OMAP_UART1_BASE 0x4806a000 #define OMAP_UART1_BASE 0x4806a000
#define OMAP_UART2_BASE 0x4806c000 #define OMAP_UART2_BASE 0x4806c000
#define OMAP_UART3_BASE 0x49020000 #define OMAP_UART3_BASE 0x49020000
#define OMAP_MAX_NR_PORTS 3
#elif defined(CONFIG_ARCH_OMAP4)
/* OMAP4 serial ports */
#define OMAP_UART1_BASE 0x4806a000
#define OMAP_UART2_BASE 0x4806c000
#define OMAP_UART3_BASE 0x48020000
#define OMAP_UART4_BASE 0x4806e000
#define OMAP_MAX_NR_PORTS 4
#endif #endif
#define OMAP_MAX_NR_PORTS 3
#define OMAP1510_BASE_BAUD (12000000/16) #define OMAP1510_BASE_BAUD (12000000/16)
#define OMAP16XX_BASE_BAUD (48000000/16) #define OMAP16XX_BASE_BAUD (48000000/16)
#define OMAP24XX_BASE_BAUD (48000000/16) #define OMAP24XX_BASE_BAUD (48000000/16)
......
/*
* Common io.c file
* This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h> #include <linux/module.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mm.h> #include <linux/mm.h>
...@@ -7,6 +18,7 @@ ...@@ -7,6 +18,7 @@
#include <mach/omap16xx.h> #include <mach/omap16xx.h>
#include <mach/omap24xx.h> #include <mach/omap24xx.h>
#include <mach/omap34xx.h> #include <mach/omap34xx.h>
#include <mach/omap44xx.h>
#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz))) #define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst))) #define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
...@@ -92,7 +104,22 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) ...@@ -92,7 +104,22 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT); return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
} }
#endif #endif
#ifdef CONFIG_ARCH_OMAP4
if (cpu_is_omap44xx()) {
if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
}
#endif
return __arm_ioremap(p, size, type); return __arm_ioremap(p, size, type);
} }
EXPORT_SYMBOL(omap_ioremap); EXPORT_SYMBOL(omap_ioremap);
......
...@@ -54,6 +54,9 @@ int __init_or_module omap_cfg_reg(const unsigned long index) ...@@ -54,6 +54,9 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
{ {
struct pin_config *reg; struct pin_config *reg;
if (cpu_is_omap44xx())
return 0;
if (mux_cfg == NULL) { if (mux_cfg == NULL) {
printk(KERN_ERR "Pin mux table not initialized\n"); printk(KERN_ERR "Pin mux table not initialized\n");
return -ENODEV; return -ENODEV;
......
...@@ -6,6 +6,9 @@ ...@@ -6,6 +6,9 @@
* Copyright (C) 2005 Nokia Corporation * Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com> * Written by Tony Lindgren <tony@atomide.com>
* *
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
...@@ -44,6 +47,8 @@ ...@@ -44,6 +47,8 @@
#define OMAP3_SRAM_VA 0xd7000000 #define OMAP3_SRAM_VA 0xd7000000
#define OMAP3_SRAM_PUB_PA 0x40208000 #define OMAP3_SRAM_PUB_PA 0x40208000
#define OMAP3_SRAM_PUB_VA 0xd7008000 #define OMAP3_SRAM_PUB_VA 0xd7008000
#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/
#define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define SRAM_BOOTLOADER_SZ 0x00 #define SRAM_BOOTLOADER_SZ 0x00
...@@ -87,6 +92,10 @@ static int is_sram_locked(void) ...@@ -87,6 +92,10 @@ static int is_sram_locked(void)
{ {
int type = 0; int type = 0;
if (cpu_is_omap44xx())
/* Not yet supported */
return 0;
if (cpu_is_omap242x()) if (cpu_is_omap242x())
type = omap_rev() & OMAP2_DEVICETYPE_MASK; type = omap_rev() & OMAP2_DEVICETYPE_MASK;
...@@ -135,6 +144,10 @@ void __init omap_detect_sram(void) ...@@ -135,6 +144,10 @@ void __init omap_detect_sram(void)
omap_sram_base = OMAP3_SRAM_VA; omap_sram_base = OMAP3_SRAM_VA;
omap_sram_start = OMAP3_SRAM_PA; omap_sram_start = OMAP3_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */ omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap44xx()) {
omap_sram_base = OMAP4_SRAM_VA;
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0x8000; /* 32K */
} else { } else {
omap_sram_base = OMAP2_SRAM_VA; omap_sram_base = OMAP2_SRAM_VA;
omap_sram_start = OMAP2_SRAM_PA; omap_sram_start = OMAP2_SRAM_PA;
...@@ -212,6 +225,12 @@ void __init omap_map_sram(void) ...@@ -212,6 +225,12 @@ void __init omap_map_sram(void)
omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
} }
if (cpu_is_omap44xx()) {
omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
base = OMAP4_SRAM_PA;
base = ROUND_DOWN(base, PAGE_SIZE);
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
}
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
...@@ -401,6 +420,8 @@ int __init omap_sram_init(void) ...@@ -401,6 +420,8 @@ int __init omap_sram_init(void)
omap243x_sram_init(); omap243x_sram_init();
else if (cpu_is_omap34xx()) else if (cpu_is_omap34xx())
omap34xx_sram_init(); omap34xx_sram_init();
else if (cpu_is_omap44xx())
omap34xx_sram_init(); /* FIXME: */
return 0; return 0;
} }
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment