Commit d2796743 authored by Mark Einon's avatar Mark Einon Committed by Greg Kroah-Hartman

staging: et131x: Put all .c files into one big file

Created one big .c file for the driver, moving the contents of all
driver .c files into it.
Signed-off-by: default avatarMark Einon <mark.einon@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent cd8eca6f
......@@ -3,14 +3,3 @@
#
obj-$(CONFIG_ET131X) += et131x.o
et131x-y := et1310_eeprom.o \
et1310_mac.o \
et1310_phy.o \
et1310_pm.o \
et1310_rx.o \
et1310_tx.o \
et131x_initpci.o \
et131x_ethtool.o \
et131x_isr.o \
et131x_netdev.o
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
*
*------------------------------------------------------------------------------
*
* et1310_pm.c - All power management related code (not completely implemented)
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_rx.h"
#include "et131x_adapter.h"
#include "et131x.h"
/**
* et1310_in_phy_coma - check if the device is in phy coma
* @adapter: pointer to our adapter structure
*
* Returns 0 if the device is not in phy coma, 1 if it is in phy coma
*/
int et1310_in_phy_coma(struct et131x_adapter *adapter)
{
u32 pmcsr;
pmcsr = readl(&adapter->regs->global.pm_csr);
return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
}
/**
* et1310_enable_phy_coma - called when network cable is unplugged
* @adapter: pointer to our adapter structure
*
* driver receive an phy status change interrupt while in D0 and check that
* phy_status is down.
*
* -- gate off JAGCore;
* -- set gigE PHY in Coma mode
* -- wake on phy_interrupt; Perform software reset JAGCore,
* re-initialize jagcore and gigE PHY
*
* Add D0-ASPM-PhyLinkDown Support:
* -- while in D0, when there is a phy_interrupt indicating phy link
* down status, call the MPSetPhyComa routine to enter this active
* state power saving mode
* -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
* indicating linkup status, call the MPDisablePhyComa routine to
* restore JAGCore and gigE PHY
*/
void et1310_enable_phy_coma(struct et131x_adapter *adapter)
{
unsigned long flags;
u32 pmcsr;
pmcsr = readl(&adapter->regs->global.pm_csr);
/* Save the GbE PHY speed and duplex modes. Need to restore this
* when cable is plugged back in
*/
/*
* TODO - when PM is re-enabled, check if we need to
* perform a similar task as this -
* adapter->pdown_speed = adapter->ai_force_speed;
* adapter->pdown_duplex = adapter->ai_force_duplex;
*/
/* Stop sending packets. */
spin_lock_irqsave(&adapter->send_hw_lock, flags);
adapter->flags |= fMP_ADAPTER_LOWER_POWER;
spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
/* Wait for outstanding Receive packets */
et131x_disable_txrx(adapter->netdev);
/* Gate off JAGCore 3 clock domains */
pmcsr &= ~ET_PMCSR_INIT;
writel(pmcsr, &adapter->regs->global.pm_csr);
/* Program gigE PHY in to Coma mode */
pmcsr |= ET_PM_PHY_SW_COMA;
writel(pmcsr, &adapter->regs->global.pm_csr);
}
/**
* et1310_disable_phy_coma - Disable the Phy Coma Mode
* @adapter: pointer to our adapter structure
*/
void et1310_disable_phy_coma(struct et131x_adapter *adapter)
{
u32 pmcsr;
pmcsr = readl(&adapter->regs->global.pm_csr);
/* Disable phy_sw_coma register and re-enable JAGCore clocks */
pmcsr |= ET_PMCSR_INIT;
pmcsr &= ~ET_PM_PHY_SW_COMA;
writel(pmcsr, &adapter->regs->global.pm_csr);
/* Restore the GbE PHY speed and duplex modes;
* Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
*/
/* TODO - when PM is re-enabled, check if we need to
* perform a similar task as this -
* adapter->ai_force_speed = adapter->pdown_speed;
* adapter->ai_force_duplex = adapter->pdown_duplex;
*/
/* Re-initialize the send structures */
et131x_init_send(adapter);
/* Reset the RFD list and re-start RU */
et131x_reset_recv(adapter);
/* Bring the device back to the state it was during init prior to
* autonegotiation being complete. This way, when we get the auto-neg
* complete interrupt, we can complete init by calling ConfigMacREGS2.
*/
et131x_soft_reset(adapter);
/* setup et1310 as per the documentation ?? */
et131x_adapter_setup(adapter);
/* Allow Tx to restart */
adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
et131x_enable_txrx(adapter->netdev);
}
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/*
* Merged from files
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
......@@ -51,6 +49,66 @@
#define DRIVER_NAME "et131x"
#define DRIVER_VERSION "v2.0"
/* EEPROM defines */
/* LBCIF Register Groups (addressed via 32-bit offsets) */
#define LBCIF_DWORD0_GROUP 0xAC
#define LBCIF_DWORD1_GROUP 0xB0
/* LBCIF Registers (addressed via 8-bit offsets) */
#define LBCIF_ADDRESS_REGISTER 0xAC
#define LBCIF_DATA_REGISTER 0xB0
#define LBCIF_CONTROL_REGISTER 0xB1
#define LBCIF_STATUS_REGISTER 0xB2
/* LBCIF Control Register Bits */
#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
#define LBCIF_CONTROL_PAGE_WRITE 0x02
#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
#define LBCIF_CONTROL_I2C_WRITE 0x40
#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
/* LBCIF Status Register Bits */
#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
#define LBCIF_STATUS_I2C_IDLE 0x02
#define LBCIF_STATUS_ACK_ERROR 0x04
#define LBCIF_STATUS_GENERAL_ERROR 0x08
#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
#define LBCIF_STATUS_EEPROM_PRESENT 0x80
/* Miscellaneous Constraints */
#define MAX_NUM_REGISTER_POLLS 1000
#define MAX_NUM_WRITE_RETRIES 2
/* MAC defines */
#define COUNTER_WRAP_16_BIT 0x10000
#define COUNTER_WRAP_12_BIT 0x1000
/* PCI defines */
#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
/* ISR defines */
/*
* For interrupts, normal running is:
* rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
* watchdog_interrupt & txdma_xfer_done
*
* In both cases, when flow control is enabled for either Tx or bi-direction,
* we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
* buffer rings are running low.
*/
#define INT_MASK_DISABLE 0xffffffff
/* NOTE: Masking out MAC_STAT Interrupt for now...
* #define INT_MASK_ENABLE 0xfff6bf17
* #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
*/
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
/* et131x_eeprom.c */
int et131x_init_eeprom(struct et131x_adapter *adapter);
......
/*
* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "et131x_defs.h"
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/ethtool.h>
#include <linux/phy.h>
#include <linux/pci.h>
#include "et131x_adapter.h"
#include "et1310_phy.h"
#include "et131x.h"
static int et131x_get_settings(struct net_device *netdev,
struct ethtool_cmd *cmd)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
return phy_ethtool_gset(adapter->phydev, cmd);
}
static int et131x_set_settings(struct net_device *netdev,
struct ethtool_cmd *cmd)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
return phy_ethtool_sset(adapter->phydev, cmd);
}
static int et131x_get_regs_len(struct net_device *netdev)
{
#define ET131X_REGS_LEN 256
return ET131X_REGS_LEN * sizeof(u32);
}
static void et131x_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *regs_data)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
struct address_map __iomem *aregs = adapter->regs;
u32 *regs_buff = regs_data;
u32 num = 0;
memset(regs_data, 0, et131x_get_regs_len(netdev));
regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
adapter->pdev->device;
/* PHY regs */
et131x_mii_read(adapter, MII_BMCR, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_BMSR, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_PHYSID1, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_PHYSID2, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_LPA, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_EXPANSION, (u16 *)&regs_buff[num++]);
/* Autoneg next page transmit reg */
et131x_mii_read(adapter, 0x07, (u16 *)&regs_buff[num++]);
/* Link partner next page reg */
et131x_mii_read(adapter, 0x08, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_CTRL1000, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_STAT1000, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, MII_ESTATUS, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_CONFIG, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
(u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LED_1, (u16 *)&regs_buff[num++]);
et131x_mii_read(adapter, PHY_LED_2, (u16 *)&regs_buff[num++]);
/* Global regs */
regs_buff[num++] = readl(&aregs->global.txq_start_addr);
regs_buff[num++] = readl(&aregs->global.txq_end_addr);
regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
regs_buff[num++] = readl(&aregs->global.pm_csr);
regs_buff[num++] = adapter->stats.interrupt_status;
regs_buff[num++] = readl(&aregs->global.int_mask);
regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
regs_buff[num++] = readl(&aregs->global.int_status_alias);
regs_buff[num++] = readl(&aregs->global.sw_reset);
regs_buff[num++] = readl(&aregs->global.slv_timer);
regs_buff[num++] = readl(&aregs->global.msi_config);
regs_buff[num++] = readl(&aregs->global.loopback);
regs_buff[num++] = readl(&aregs->global.watchdog_timer);
/* TXDMA regs */
regs_buff[num++] = readl(&aregs->txdma.csr);
regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
regs_buff[num++] = readl(&aregs->txdma.service_request);
regs_buff[num++] = readl(&aregs->txdma.service_complete);
regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
/* RXDMA regs */
regs_buff[num++] = readl(&aregs->rxdma.csr);
regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
}
#define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
static void et131x_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *info)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
}
static struct ethtool_ops et131x_ethtool_ops = {
.get_settings = et131x_get_settings,
.set_settings = et131x_set_settings,
.get_drvinfo = et131x_get_drvinfo,
.get_regs_len = et131x_get_regs_len,
.get_regs = et131x_get_regs,
.get_link = ethtool_op_get_link,
};
void et131x_set_ethtool_ops(struct net_device *netdev)
{
SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
}
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