Commit d2982748 authored by Thierry Reding's avatar Thierry Reding

drm/tegra: dc: Check for valid parent clock

Check that the desired parent clock is indeed a valid parent for the
display controller clock. This is purely cosmetic at this point since
the parent clocks are specified in DT and all the currently defined
parents are in fact valid parents of the display controller clock.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 13a7a6ac
...@@ -1177,6 +1177,9 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, ...@@ -1177,6 +1177,9 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc,
{ {
struct tegra_dc_state *state = to_dc_state(crtc_state); struct tegra_dc_state *state = to_dc_state(crtc_state);
if (!clk_has_parent(dc->clk, clk))
return -EINVAL;
state->clk = clk; state->clk = clk;
state->pclk = pclk; state->pclk = pclk;
state->div = div; state->div = div;
......
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