Commit d4a415dc authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Fix MST oops due to MSA changes

The MSA MISC computation now depends on the connector state, and
we do it from the DDI .pre_enable() hook. All that is fine for
DP SST but with MST we don't actually pass the connector state
to the dig port's .pre_enable() hook which leads to an oops.

Need to think more how to solve this in a cleaner fashion, but
for now let's just add a NULL check to stop the oopsing.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Fixes: 0c06fa15 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP MSA")
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015190538.27539-1-ville.syrjala@linux.intel.comReviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
parent 05488673
...@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, ...@@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
* of Color Encoding Format and Content Color Gamut] while sending * of Color Encoding Format and Content Color Gamut] while sending
* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
*
* FIXME MST doesn't pass in the conn_state
*/ */
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
temp |= DP_MSA_MISC_COLOR_VSC_SDP; temp |= DP_MSA_MISC_COLOR_VSC_SDP;
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment