drm/nouveau/mc: abstract interface to master intr registers

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h

@@ -10,6 +10,9 @@ struct nvkm_mc {
 	bool use_msi;
 };
 
+void nvkm_mc_intr_unarm(struct nvkm_mc *);
+void nvkm_mc_intr_rearm(struct nvkm_mc *);
+u32 nvkm_mc_intr_mask(struct nvkm_mc *);
 void nvkm_mc_unk260(struct nvkm_mc *, u32 data);
 
 int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **);

drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c

@@ -32,13 +32,24 @@ nvkm_mc_unk260(struct nvkm_mc *mc, u32 data)
 		mc->func->unk260(mc, data);
 }
 
-static inline u32
+void
+nvkm_mc_intr_unarm(struct nvkm_mc *mc)
+{
+	return mc->func->intr_unarm(mc);
+}
+
+void
+nvkm_mc_intr_rearm(struct nvkm_mc *mc)
+{
+	return mc->func->intr_rearm(mc);
+}
+
+u32
 nvkm_mc_intr_mask(struct nvkm_mc *mc)
 {
-	struct nvkm_device *device = mc->subdev.device;
-	u32 intr = nvkm_rd32(device, 0x000100);
-	if (intr == 0xffffffff) /* likely fallen off the bus */
-		intr = 0x00000000;
+	u32 intr = mc->func->intr_mask(mc);
+	if (WARN_ON_ONCE(intr == 0xffffffff))
+		intr = 0; /* likely fallen off the bus */
 	return intr;
 }
 
@@ -52,8 +63,7 @@ nvkm_mc_intr(int irq, void *arg)
 	struct nvkm_subdev *unit;
 	u32 intr;
 
-	nvkm_wr32(device, 0x000140, 0x00000000);
-	nvkm_rd32(device, 0x000140);
+	nvkm_mc_intr_unarm(mc);
 	intr = nvkm_mc_intr_mask(mc);
 	if (mc->use_msi)
 		mc->func->msi_rearm(mc);
@@ -74,14 +84,15 @@ nvkm_mc_intr(int irq, void *arg)
 			nvkm_error(subdev, "unknown intr %08x\n", stat);
 	}
 
-	nvkm_wr32(device, 0x000140, 0x00000001);
+	nvkm_mc_intr_rearm(mc);
 	return intr ? IRQ_HANDLED : IRQ_NONE;
 }
 
 static int
 nvkm_mc_fini(struct nvkm_subdev *subdev, bool suspend)
 {
-	nvkm_wr32(subdev->device, 0x000140, 0x00000000);
+	struct nvkm_mc *mc = nvkm_mc(subdev);
+	nvkm_mc_intr_unarm(mc);
 	return 0;
 }
 
@@ -96,10 +107,9 @@ static int
 nvkm_mc_init(struct nvkm_subdev *subdev)
 {
 	struct nvkm_mc *mc = nvkm_mc(subdev);
-	struct nvkm_device *device = mc->subdev.device;
 	if (mc->func->init)
 		mc->func->init(mc);
-	nvkm_wr32(device, 0x000140, 0x00000001);
+	nvkm_mc_intr_rearm(mc);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c

@@ -27,6 +27,9 @@ static const struct nvkm_mc_func
 g94_mc = {
 	.init = nv50_mc_init,
 	.intr = nv50_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv40_mc_msi_rearm,
 };
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c

@@ -48,6 +48,9 @@ static const struct nvkm_mc_func
 g98_mc = {
 	.init = nv50_mc_init,
 	.intr = g98_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv40_mc_msi_rearm,
 };
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c

@@ -64,6 +64,9 @@ static const struct nvkm_mc_func
 gf100_mc = {
 	.init = nv50_mc_init,
 	.intr = gf100_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = gf100_mc_msi_rearm,
 	.unk260 = gf100_mc_unk260,
 };

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c

@@ -27,6 +27,9 @@ static const struct nvkm_mc_func
 gf106_mc = {
 	.init = nv50_mc_init,
 	.intr = gf100_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv40_mc_msi_rearm,
 	.unk260 = gf100_mc_unk260,
 };

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c

@@ -27,6 +27,9 @@ static const struct nvkm_mc_func
 gk20a_mc = {
 	.init = nv50_mc_init,
 	.intr = gf100_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv40_mc_msi_rearm,
 };
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c

@@ -38,6 +38,27 @@ nv04_mc_intr[] = {
 	{}
 };
 
+void
+nv04_mc_intr_unarm(struct nvkm_mc *mc)
+{
+	struct nvkm_device *device = mc->subdev.device;
+	nvkm_wr32(device, 0x000140, 0x00000000);
+	nvkm_rd32(device, 0x000140);
+}
+
+void
+nv04_mc_intr_rearm(struct nvkm_mc *mc)
+{
+	struct nvkm_device *device = mc->subdev.device;
+	nvkm_wr32(device, 0x000140, 0x00000001);
+}
+
+u32
+nv04_mc_intr_mask(struct nvkm_mc *mc)
+{
+	return nvkm_rd32(mc->subdev.device, 0x000100);
+}
+
 void
 nv04_mc_init(struct nvkm_mc *mc)
 {
@@ -50,6 +71,9 @@ static const struct nvkm_mc_func
 nv04_mc = {
 	.init = nv04_mc_init,
 	.intr = nv04_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 };
 
 int

drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c

@@ -33,6 +33,9 @@ static const struct nvkm_mc_func
 nv40_mc = {
 	.init = nv04_mc_init,
 	.intr = nv04_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv40_mc_msi_rearm,
 };
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c

@@ -41,6 +41,9 @@ static const struct nvkm_mc_func
 nv44_mc = {
 	.init = nv44_mc_init,
 	.intr = nv04_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv40_mc_msi_rearm,
 };
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c

@@ -27,6 +27,9 @@ static const struct nvkm_mc_func
 nv4c_mc = {
 	.init = nv44_mc_init,
 	.intr = nv04_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 };
 
 int

drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c

@@ -59,6 +59,9 @@ static const struct nvkm_mc_func
 nv50_mc = {
 	.init = nv50_mc_init,
 	.intr = nv50_mc_intr,
+	.intr_unarm = nv04_mc_intr_unarm,
+	.intr_rearm = nv04_mc_intr_rearm,
+	.intr_mask = nv04_mc_intr_mask,
 	.msi_rearm = nv50_mc_msi_rearm,
 };
 

drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h

@@ -14,12 +14,21 @@ struct nvkm_mc_intr {
 struct nvkm_mc_func {
 	void (*init)(struct nvkm_mc *);
 	const struct nvkm_mc_intr *intr;
+	/* disable reporting of interrupts to host */
+	void (*intr_unarm)(struct nvkm_mc *);
+	/* enable reporting of interrupts to host */
+	void (*intr_rearm)(struct nvkm_mc *);
+	/* retrieve pending interrupt mask (NV_PMC_INTR) */
+	u32 (*intr_mask)(struct nvkm_mc *);
 	void (*msi_rearm)(struct nvkm_mc *);
 	void (*unk260)(struct nvkm_mc *, u32);
 };
 
 void nv04_mc_init(struct nvkm_mc *);
 extern const struct nvkm_mc_intr nv04_mc_intr[];
+void nv04_mc_intr_unarm(struct nvkm_mc *);
+void nv04_mc_intr_rearm(struct nvkm_mc *);
+u32 nv04_mc_intr_mask(struct nvkm_mc *);
 
 void nv40_mc_msi_rearm(struct nvkm_mc *);