drm/fsl-dcu: fix endian issue when using clk_register_divider
commit 6cc4758a upstream. Since using clk_register_divider to setup the pixel clock, regmap is no longer used. Regmap did take care of DCU using different endianness. Check endianness using the device-tree property "big-endian" to determine the location of DIV_RATIO. Fixes: 2d701449 ("drm/fsl-dcu: use common clock framework for pixel clock divider") Reported-by:Meng Yi <meng.yi@nxp.com> Signed-off-by:
Stefan Agner <stefan@agner.ch> Tested-by:
Meng Yi <meng.yi@nxp.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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