Commit d7adfe5f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dinh Nguyen

ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:
    l2-cache@fffff000: $nodename:0:
        'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Fixes: 475dc86d ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 3bf9b8ff
...@@ -726,7 +726,7 @@ ocram-ecc@ffd08144 { ...@@ -726,7 +726,7 @@ ocram-ecc@ffd08144 {
}; };
}; };
L2: l2-cache@fffef000 { L2: cache-controller@fffef000 {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>; reg = <0xfffef000 0x1000>;
interrupts = <0 38 0x04>; interrupts = <0 38 0x04>;
......
...@@ -636,7 +636,7 @@ sdr: sdr@ffcfb100 { ...@@ -636,7 +636,7 @@ sdr: sdr@ffcfb100 {
reg = <0xffcfb100 0x80>; reg = <0xffcfb100 0x80>;
}; };
L2: l2-cache@fffff000 { L2: cache-controller@fffff000 {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>; reg = <0xfffff000 0x1000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
......
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