Commit d8020bee authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar

perf/x86/intel: Handle new arch perfmon v4 status bits

ArchPerfmon v4 has some new status bits in GLOBAL_STATUS.

These need to be ignored when deciding whether a NMI
was an NMI, to avoid eating all NMIs when they
stay set, see:

    b292d7a1 ("perf/x86/intel: ignore CondChgd bit to avoid false NMI handling")

This patch ignores the new ASIF bit, which indicates
that SGX interfered with the PMU, and also the new
LBR freezing bits, which are set when the LBRs get
frozen, plus the existing CondChange (set by JTAG
debuggers and some buggy BIOSes)
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1431285767-27027-8-git-send-email-andi@firstfloor.orgSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 50eab8f6
...@@ -1611,13 +1611,14 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) ...@@ -1611,13 +1611,14 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
intel_pmu_lbr_read(); intel_pmu_lbr_read();
/* /*
* CondChgd bit 63 doesn't mean any overflow status. Ignore * Ignore a range of extra bits in status that do not indicate
* and clear the bit. * overflow by themselves.
*/ */
if (__test_and_clear_bit(63, (unsigned long *)&status)) { status &= ~(GLOBAL_STATUS_COND_CHG |
if (!status) GLOBAL_STATUS_ASIF |
goto done; GLOBAL_STATUS_LBRS_FROZEN);
} if (!status)
goto done;
/* /*
* PEBS overflow sets bit 62 in the global status register * PEBS overflow sets bit 62 in the global status register
......
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