Commit d9c3f5df authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Chris Ball

dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.

Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Finally, fix an indentation error for the sysmgr node.
Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Acked-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent ec1e5d70
* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile
Storage Host Controller
The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific
extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:
* compatible: should be
- "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform
Example:
mmc: dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0 129 4>;
#address-cells = <1>;
#size-cells = <0>;
};
...@@ -473,6 +473,17 @@ L2: l2-cache@fffef000 { ...@@ -473,6 +473,17 @@ L2: l2-cache@fffef000 {
arm,data-latency = <2 1 1>; arm,data-latency = <2 1 1>;
}; };
mmc: dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0 139 4>;
fifo-depth = <0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
};
/* Local timer */ /* Local timer */
timer@fffec600 { timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
...@@ -527,8 +538,8 @@ rstmgr@ffd05000 { ...@@ -527,8 +538,8 @@ rstmgr@ffd05000 {
}; };
sysmgr@ffd08000 { sysmgr@ffd08000 {
compatible = "altr,sys-mgr"; compatible = "altr,sys-mgr", "syscon";
reg = <0xffd08000 0x4000>; reg = <0xffd08000 0x4000>;
}; };
}; };
}; };
...@@ -27,6 +27,17 @@ osc1 { ...@@ -27,6 +27,17 @@ osc1 {
}; };
}; };
dwmmc0@ff704000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
serial0@ffc02000 { serial0@ffc02000 {
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
......
...@@ -28,6 +28,17 @@ osc1 { ...@@ -28,6 +28,17 @@ osc1 {
}; };
}; };
dwmmc0@ff704000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
ethernet@ff702000 { ethernet@ff702000 {
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */ phy-addr = <0xffffffff>; /* probe for phy addr */
......
...@@ -41,6 +41,17 @@ osc1 { ...@@ -41,6 +41,17 @@ osc1 {
}; };
}; };
dwmmc0@ff704000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
ethernet@ff700000 { ethernet@ff700000 {
phy-mode = "gmii"; phy-mode = "gmii";
status = "okay"; status = "okay";
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment