Commit dad4acc8 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher

drm/amdgpu/gfx8: Tidy up various PG helpers

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 216cde60
...@@ -5257,20 +5257,15 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade ...@@ -5257,20 +5257,15 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade
enable ? enable ?
AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
if (enable) { temp = data = RREG32(mmRLC_PG_CNTL);
/* Enable static MGPG */ /* Enable static MGPG */
temp = data = RREG32(mmRLC_PG_CNTL); if (enable)
data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
else
if (temp != data)
WREG32(mmRLC_PG_CNTL, data);
} else {
temp = data = RREG32(mmRLC_PG_CNTL);
data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
if (temp != data) if (temp != data)
WREG32(mmRLC_PG_CNTL, data); WREG32(mmRLC_PG_CNTL, data);
}
} }
static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
...@@ -5278,20 +5273,15 @@ static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad ...@@ -5278,20 +5273,15 @@ static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
{ {
uint32_t data, temp; uint32_t data, temp;
if (enable) { temp = data = RREG32(mmRLC_PG_CNTL);
/* Enable dynamic MGPG */ /* Enable dynamic MGPG */
temp = data = RREG32(mmRLC_PG_CNTL); if (enable)
data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
else
if (temp != data)
WREG32(mmRLC_PG_CNTL, data);
} else {
temp = data = RREG32(mmRLC_PG_CNTL);
data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
if (temp != data) if (temp != data)
WREG32(mmRLC_PG_CNTL, data); WREG32(mmRLC_PG_CNTL, data);
}
} }
static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
...@@ -5299,20 +5289,15 @@ static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *ade ...@@ -5299,20 +5289,15 @@ static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *ade
{ {
uint32_t data, temp; uint32_t data, temp;
if (enable) { temp = data = RREG32(mmRLC_PG_CNTL);
/* Enable quick PG */ /* Enable quick PG */
temp = data = RREG32(mmRLC_PG_CNTL); if (enable)
data |= 0x100000; data |= 0x100000;
else
if (temp != data)
WREG32(mmRLC_PG_CNTL, data);
} else {
temp = data = RREG32(mmRLC_PG_CNTL);
data &= ~0x100000; data &= ~0x100000;
if (temp != data) if (temp != data)
WREG32(mmRLC_PG_CNTL, data); WREG32(mmRLC_PG_CNTL, data);
}
} }
static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev, static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
......
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