Commit daec765d authored by Neil Zhang's avatar Neil Zhang Committed by Felipe Balbi

usb: gadget: mv_udc: fix dtd dma confusion

The controller will prime failure sometimes when do the iperf test.
Add delay to wait controller release dtd dma before we free it.
Then the issue is gone.
Signed-off-by: default avatarNeil Zhang <zhangwm@marvell.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 046b07ac
...@@ -138,6 +138,7 @@ static int process_ep_req(struct mv_udc *udc, int index, ...@@ -138,6 +138,7 @@ static int process_ep_req(struct mv_udc *udc, int index,
int i, direction; int i, direction;
int retval = 0; int retval = 0;
u32 errors; u32 errors;
u32 bit_pos;
curr_dqh = &udc->ep_dqh[index]; curr_dqh = &udc->ep_dqh[index];
direction = index % 2; direction = index % 2;
...@@ -155,10 +156,20 @@ static int process_ep_req(struct mv_udc *udc, int index, ...@@ -155,10 +156,20 @@ static int process_ep_req(struct mv_udc *udc, int index,
errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK; errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
if (!errors) { if (!errors) {
remaining_length += remaining_length =
(curr_dtd->size_ioc_sts & DTD_PACKET_SIZE) (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
>> DTD_LENGTH_BIT_POS; >> DTD_LENGTH_BIT_POS;
actual -= remaining_length; actual -= remaining_length;
if (remaining_length) {
if (direction) {
dev_dbg(&udc->dev->dev,
"TX dTD remains data\n");
retval = -EPROTO;
break;
} else
break;
}
} else { } else {
dev_info(&udc->dev->dev, dev_info(&udc->dev->dev,
"complete_tr error: ep=%d %s: error = 0x%x\n", "complete_tr error: ep=%d %s: error = 0x%x\n",
...@@ -180,6 +191,20 @@ static int process_ep_req(struct mv_udc *udc, int index, ...@@ -180,6 +191,20 @@ static int process_ep_req(struct mv_udc *udc, int index,
if (retval) if (retval)
return retval; return retval;
if (direction == EP_DIR_OUT)
bit_pos = 1 << curr_req->ep->ep_num;
else
bit_pos = 1 << (16 + curr_req->ep->ep_num);
while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
while (readl(&udc->op_regs->epstatus) & bit_pos)
udelay(1);
break;
}
udelay(1);
}
curr_req->req.actual = actual; curr_req->req.actual = actual;
return 0; return 0;
......
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