Commit dc076af5 authored by Ryder Lee's avatar Ryder Lee Committed by Felix Fietkau

mt76: mt7915: overwrite qid for non-bufferable mgmt frames

Overwrite hw queue id for non-bufferable management frames if the hw/fw
support always txq (altxq) in order to be in sync with mac txwi code
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 80c99340
...@@ -79,26 +79,27 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, ...@@ -79,26 +79,27 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
} }
} }
static void
mt7915_tx_cleanup(struct mt7915_dev *dev)
{
mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
mt76_queue_tx_cleanup(dev, MT_TXQ_MCU_WA, false);
mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
}
static int mt7915_poll_tx(struct napi_struct *napi, int budget) static int mt7915_poll_tx(struct napi_struct *napi, int budget)
{ {
static const u8 queue_map[] = {
MT_TXQ_MCU,
MT_TXQ_MCU_WA,
MT_TXQ_BE
};
struct mt7915_dev *dev; struct mt7915_dev *dev;
int i;
dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); dev = container_of(napi, struct mt7915_dev, mt76.tx_napi);
for (i = 0; i < ARRAY_SIZE(queue_map); i++) mt7915_tx_cleanup(dev);
mt76_queue_tx_cleanup(dev, queue_map[i], false);
if (napi_complete_done(napi, 0)) if (napi_complete_done(napi, 0))
mt7915_irq_enable(dev, MT_INT_TX_DONE_ALL); mt7915_irq_enable(dev, MT_INT_TX_DONE_ALL);
for (i = 0; i < ARRAY_SIZE(queue_map); i++) mt7915_tx_cleanup(dev);
mt76_queue_tx_cleanup(dev, queue_map[i], false);
mt7915_mac_sta_poll(dev); mt7915_mac_sta_poll(dev);
......
...@@ -591,16 +591,16 @@ void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, ...@@ -591,16 +591,16 @@ void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) { if (beacon) {
q_idx = wmm_idx * MT7915_MAX_WMM_SETS +
mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb));
p_fmt = MT_TX_TYPE_CT;
} else if (beacon) {
q_idx = MT_LMAC_BCN0;
p_fmt = MT_TX_TYPE_FW; p_fmt = MT_TX_TYPE_FW;
} else { q_idx = MT_LMAC_BCN0;
} else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
p_fmt = MT_TX_TYPE_CT;
q_idx = MT_LMAC_ALTX0; q_idx = MT_LMAC_ALTX0;
} else {
p_fmt = MT_TX_TYPE_CT; p_fmt = MT_TX_TYPE_CT;
q_idx = wmm_idx * MT7915_MAX_WMM_SETS +
mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb));
} }
val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
...@@ -616,6 +616,7 @@ void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, ...@@ -616,6 +616,7 @@ void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
FIELD_PREP(MT_TXD1_TID, FIELD_PREP(MT_TXD1_TID,
skb->priority & IEEE80211_QOS_CTL_TID_MASK) | skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0)
val |= MT_TXD1_TGID; val |= MT_TXD1_TGID;
......
...@@ -103,7 +103,7 @@ static int mt7915_pci_probe(struct pci_dev *pdev, ...@@ -103,7 +103,7 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
static const struct mt76_driver_ops drv_ops = { static const struct mt76_driver_ops drv_ops = {
/* txwi_size = txd size + txp size */ /* txwi_size = txd size + txp size */
.txwi_size = MT_TXD_SIZE + sizeof(struct mt7915_txp), .txwi_size = MT_TXD_SIZE + sizeof(struct mt7915_txp),
.drv_flags = MT_DRV_TXWI_NO_FREE, .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
.survey_flags = SURVEY_INFO_TIME_TX | .survey_flags = SURVEY_INFO_TIME_TX |
SURVEY_INFO_TIME_RX | SURVEY_INFO_TIME_RX |
SURVEY_INFO_TIME_BSS_RX, SURVEY_INFO_TIME_BSS_RX,
......
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