Commit dc9c8e21 authored by Wei Ni's avatar Wei Ni Committed by Jaroslav Kysela

ALSA: Fix for reading RIRB buffer on NVIDIA aza controller with AMD Phenom cpu

When read RIRB buffer immediately after RIRB interrupt received,
sometimes the data will be "0x0". If we wait for some time, the data
in buffer will be correct. This issue only occurred with AMD Phenom cpu.
So we set this "needs_damn_long_delay" flag.
Signed-off-by: default avatarWei Ni <wni@nvidia.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
Signed-off-by: default avatarJaroslav Kysela <perex@perex.cz>
parent 9a10eb21
...@@ -1220,6 +1220,9 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model, ...@@ -1220,6 +1220,9 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model,
if (err < 0) if (err < 0)
return err; return err;
if (chip->driver_type == AZX_DRIVER_NVIDIA)
chip->bus->needs_damn_long_delay = 1;
codecs = audio_codecs = 0; codecs = audio_codecs = 0;
max_slots = azx_max_codecs[chip->driver_type]; max_slots = azx_max_codecs[chip->driver_type];
if (!max_slots) if (!max_slots)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment