Commit dd14a330 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth Committed by Jiri Slaby

irqchip: orion: clear bridge cause register on init

commit 7b119fd1 upstream.

It is good practice to mask and clear pending irqs on init. We already
mask all irqs, so also clear the bridge irq cause register.
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
Signed-off-by: default avatarJiri Slaby <jslaby@suse.cz>
parent de77ab8e
...@@ -180,8 +180,9 @@ static int __init orion_bridge_irq_init(struct device_node *np, ...@@ -180,8 +180,9 @@ static int __init orion_bridge_irq_init(struct device_node *np,
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
/* mask all interrupts */ /* mask and clear all interrupts */
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
irq_set_handler_data(irq, domain); irq_set_handler_data(irq, domain);
irq_set_chained_handler(irq, orion_bridge_irq_handler); irq_set_chained_handler(irq, orion_bridge_irq_handler);
......
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