Commit de10e04e authored by Philipp Zabel's avatar Philipp Zabel Committed by Russell King

ARM: dts: imx51: Add IPU ports and endpoints, move imx-drm node to dtsi

This patch connects IPU and and parallel display device tree
nodes using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt

The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.

Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and panels have to be added.
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 49ba1790
...@@ -18,7 +18,6 @@ / { ...@@ -18,7 +18,6 @@ / {
display@di1 { display@di1 {
compatible = "fsl,imx-parallel-display"; compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "bgr666"; interface-pix-fmt = "bgr666";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>; pinctrl-0 = <&pinctrl_ipu_disp1_1>;
...@@ -41,6 +40,12 @@ lw700 { ...@@ -41,6 +40,12 @@ lw700 {
pixelclk-active = <0>; pixelclk-active = <0>;
}; };
}; };
port {
display_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
}; };
gpio-keys { gpio-keys {
...@@ -122,3 +127,7 @@ MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 ...@@ -122,3 +127,7 @@ MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
}; };
}; };
}; };
&ipu_di0_disp0 {
remote-endpoint = <&display_in>;
};
...@@ -23,7 +23,6 @@ memory { ...@@ -23,7 +23,6 @@ memory {
display0: display@di0 { display0: display@di0 {
compatible = "fsl,imx-parallel-display"; compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24"; interface-pix-fmt = "rgb24";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>; pinctrl-0 = <&pinctrl_ipu_disp1_1>;
...@@ -41,11 +40,16 @@ timing0: dvi { ...@@ -41,11 +40,16 @@ timing0: dvi {
vsync-len = <10>; vsync-len = <10>;
}; };
}; };
port {
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
}; };
display1: display@di1 { display1: display@di1 {
compatible = "fsl,imx-parallel-display"; compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565"; interface-pix-fmt = "rgb565";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>; pinctrl-0 = <&pinctrl_ipu_disp2_1>;
...@@ -68,6 +72,12 @@ timing1: claawvga { ...@@ -68,6 +72,12 @@ timing1: claawvga {
pixelclk-active = <0>; pixelclk-active = <0>;
}; };
}; };
port {
display1_in: endpoint {
remote-endpoint = <&ipu_di1_disp1>;
};
};
}; };
gpio-keys { gpio-keys {
...@@ -81,12 +91,6 @@ power { ...@@ -81,12 +91,6 @@ power {
}; };
}; };
imx-drm {
compatible = "fsl,imx-drm";
crtcs = <&ipu 0>, <&ipu 1>;
connectors = <&display0>, <&display1>;
};
sound { sound {
compatible = "fsl,imx51-babbage-sgtl5000", compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000"; "fsl,imx-audio-sgtl5000";
...@@ -264,6 +268,14 @@ partition@40000 { ...@@ -264,6 +268,14 @@ partition@40000 {
}; };
}; };
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&ipu_di1_disp1 {
remote-endpoint = <&display1_in>;
};
&ssi2 { &ssi2 {
fsl,mode = "i2s-slave"; fsl,mode = "i2s-slave";
status = "okay"; status = "okay";
......
...@@ -79,6 +79,11 @@ cpu@0 { ...@@ -79,6 +79,11 @@ cpu@0 {
}; };
}; };
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>, <&ipu_di1>;
};
soc { soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -92,13 +97,28 @@ iram: iram@1ffe0000 { ...@@ -92,13 +97,28 @@ iram: iram@1ffe0000 {
}; };
ipu: ipu@40000000 { ipu: ipu@40000000 {
#crtc-cells = <1>; #address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ipu"; compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>; reg = <0x40000000 0x20000000>;
interrupts = <11 10>; interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>; clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clock-names = "bus", "di0", "di1"; clock-names = "bus", "di0", "di1";
resets = <&src 2>; resets = <&src 2>;
ipu_di0: port@2 {
reg = <2>;
ipu_di0_disp0: endpoint {
};
};
ipu_di1: port@3 {
reg = <3>;
ipu_di1_disp1: endpoint {
};
};
}; };
aips@70000000 { /* AIPS1 */ aips@70000000 { /* AIPS1 */
......
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