PPC: Make Motorola CPM2 I/O core support more generic.

It's used on more than one CPU.

arch/ppc/8260_io/Kconfig

 #
-# MPC8260 Communication options
+# CPM2 Communication options
 #
 
-menu "MPC8260 CPM Options"
-	depends on 8260
+menu "CPM2 Options"
+	depends on CPM2
 
 config SCC_CONSOLE
 	bool "Enable SCC Console"
@@ -24,19 +24,19 @@ config FCC1_ENET
 	bool "Ethernet on FCC1"
 	depends on FEC_ENET
 	help
-	  Use MPC8260 fast Ethernet controller 1 to drive Ethernet (default).
+	  Use CPM2 fast Ethernet controller 1 to drive Ethernet (default).
 
 config FCC2_ENET
 	bool "Ethernet on FCC2"
 	depends on FEC_ENET
 	help
-	  Use MPC8260 fast Ethernet controller 2 to drive Ethernet.
+	  Use CPM2 fast Ethernet controller 2 to drive Ethernet.
 
 config FCC3_ENET
 	bool "Ethernet on FCC3"
 	depends on FEC_ENET
 	help
-	  Use MPC8260 fast Ethernet controller 3 to drive Ethernet.
+	  Use CPM2 fast Ethernet controller 3 to drive Ethernet.
 
 config USE_MDIO
 	bool "Use MDIO for PHY configuration"

arch/ppc/8260_io/Makefile

 #
-# Makefile for the linux MPC8xx ppc-specific parts of comm processor
+# Makefile for the linux ppc-specific parts of comm processor (v2)
 #
 
 obj-y			:= commproc.o uart.o

arch/ppc/8260_io/commproc.c

@@ -26,29 +26,26 @@
 #include <asm/mpc8260.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/immap_8260.h>
-#include <asm/cpm_8260.h>
+#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
 
 static	uint	dp_alloc_base;	/* Starting offset in DP ram */
 static	uint	dp_alloc_top;	/* Max offset + 1 */
 static	uint	host_buffer;	/* One page of host buffer */
 static	uint	host_end;	/* end + 1 */
-cpm8260_t	*cpmp;		/* Pointer to comm processor space */
+cpm_cpm2_t	*cpmp;		/* Pointer to comm processor space */
 
 /* We allocate this here because it is used almost exclusively for
  * the communication processor devices.
  */
-immap_t		*immr;
+cpm2_map_t *cpm2_immr;
 
 void
-m8260_cpm_reset(void)
+cpm2_reset(void)
 {
-	volatile immap_t	 *imp;
-	volatile cpm8260_t	*commproc;
-	uint			vpgaddr;
+	uint vpgaddr;
 
-	immr = imp = (volatile immap_t *)IMAP_ADDR;
-	commproc = &imp->im_cpm;
+	cpm2_immr = (cpm2_map_t *)CPM_MAP_ADDR;
 
 	/* Reclaim the DP memory for our use.
 	*/
@@ -65,7 +62,7 @@ m8260_cpm_reset(void)
 
 	/* Tell everyone where the comm processor resides.
 	*/
-	cpmp = (cpm8260_t *)commproc;
+	cpmp = &cpm2_immr->im_cpm;
 }
 
 /* Allocate some memory from the dual ported ram.
@@ -73,7 +70,7 @@ m8260_cpm_reset(void)
  * if they ask.
  */
 uint
-m8260_cpm_dpalloc(uint size, uint align)
+cpm2_dpalloc(uint size, uint align)
 {
 	uint	retloc;
 	uint	align_mask, off;
@@ -100,7 +97,7 @@ m8260_cpm_dpalloc(uint size, uint align)
  * UART "fifos" and the like.
  */
 uint
-m8260_cpm_hostalloc(uint size, uint align)
+cpm2_hostalloc(uint size, uint align)
 {
 	uint	retloc;
 	uint	align_mask, off;
@@ -140,17 +137,17 @@ m8260_cpm_hostalloc(uint size, uint align)
  * oversampled clock.
  */
 void
-m8260_cpm_setbrg(uint brg, uint rate)
+cpm2_setbrg(uint brg, uint rate)
 {
 	volatile uint	*bp;
 
 	/* This is good enough to get SMCs running.....
 	*/
 	if (brg < 4) {
-		bp = (uint *)&immr->im_brgc1;
+		bp = (uint *)&cpm2_immr->im_brgc1;
 	}
 	else {
-		bp = (uint *)&immr->im_brgc5;
+		bp = (uint *)&cpm2_immr->im_brgc5;
 		brg -= 4;
 	}
 	bp += brg;
@@ -161,15 +158,15 @@ m8260_cpm_setbrg(uint brg, uint rate)
  * clocks.
  */
 void
-m8260_cpm_fastbrg(uint brg, uint rate, int div16)
+cpm2_fastbrg(uint brg, uint rate, int div16)
 {
 	volatile uint	*bp;
 
 	if (brg < 4) {
-		bp = (uint *)&immr->im_brgc1;
+		bp = (uint *)&cpm2_immr->im_brgc1;
 	}
 	else {
-		bp = (uint *)&immr->im_brgc5;
+		bp = (uint *)&cpm2_immr->im_brgc5;
 		brg -= 4;
 	}
 	bp += brg;

arch/ppc/8260_io/enet.c

@@ -40,12 +40,12 @@
 #include <linux/skbuff.h>
 #include <linux/spinlock.h>
 
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/pgtable.h>
 #include <asm/mpc8260.h>
 #include <asm/bitops.h>
 #include <asm/uaccess.h>
-#include <asm/cpm_8260.h>
+#include <asm/cpm2.h>
 #include <asm/irq.h>
 
 /*
@@ -376,7 +376,7 @@ scc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 	    }
 
 	    if (must_restart) {
-		volatile cpm8260_t *cp;
+		volatile cpm_cpm2_t *cp;
 
 		/* Some transmit errors cause the transmitter to shut
 		 * down.  We now issue a restart transmit.  Since the
@@ -552,10 +552,10 @@ static void set_multicast_list(struct net_device *dev)
 	
 		/* Log any net taps. */
 		printk("%s: Promiscuous mode enabled.\n", dev->name);
-		cep->sccp->scc_pmsr |= SCC_PSMR_PRO;
+		cep->sccp->scc_psmr |= SCC_PSMR_PRO;
 	} else {
 
-		cep->sccp->scc_pmsr &= ~SCC_PSMR_PRO;
+		cep->sccp->scc_psmr &= ~SCC_PSMR_PRO;
 
 		if (dev->flags & IFF_ALLMULTI) {
 			/* Catch all multicast addresses, so set the
@@ -617,15 +617,15 @@ static int __init scc_enet_init(void)
 	unsigned long	mem_addr;
 	bd_t		*bd;
 	volatile	cbd_t		*bdp;
-	volatile	cpm8260_t	*cp;
+	volatile	cpm_cpm2_t	*cp;
 	volatile	scc_t		*sccp;
 	volatile	scc_enet_t	*ep;
-	volatile	immap_t		*immap;
-	volatile	iop8260_t	*io;
+	volatile	cpm2_map_t		*immap;
+	volatile	iop_cpm2_t	*io;
 
 	cp = cpmp;	/* Get pointer to Communication Processor */
 
-	immap = (immap_t *)IMAP_ADDR;	/* and to internal registers */
+	immap = (cpm2_map_t *)CPM_MAP_ADDR;	/* and to internal registers */
 	io = &immap->im_ioport;
 
 	bd = (bd_t *)__res;
@@ -680,11 +680,11 @@ static int __init scc_enet_init(void)
 	 * These are relative offsets in the DP ram address space.
 	 * Initialize base addresses for the buffer descriptors.
 	 */
-	i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
+	i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
 	ep->sen_genscc.scc_rbase = i;
 	cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
 
-	i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
+	i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
 	ep->sen_genscc.scc_tbase = i;
 	cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
 
@@ -820,7 +820,7 @@ static int __init scc_enet_init(void)
 	/* Set processing mode.  Use Ethernet CRC, catch broadcast, and
 	 * start frame search 22 bit times after RENA.
 	 */
-	sccp->scc_pmsr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
+	sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
 
 	/* It is now OK to enable the Ethernet transmitter.
 	 * Unfortunately, there are board implementation differences here.

arch/ppc/8260_io/fcc_enet.c

@@ -35,13 +35,13 @@
 #include <linux/skbuff.h>
 #include <linux/spinlock.h>
 
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/pgtable.h>
 #include <asm/mpc8260.h>
 #include <asm/irq.h>
 #include <asm/bitops.h>
 #include <asm/uaccess.h>
-#include <asm/cpm_8260.h>
+#include <asm/cpm2.h>
 
 /* The transmitter timeout
  */
@@ -331,12 +331,12 @@ struct fcc_enet_private {
 };
 
 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
-	volatile immap_t *immap);
+	volatile cpm2_map_t *immap);
 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
-static void init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
-	volatile immap_t *immap);
+static void init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
+	volatile cpm2_map_t *immap);
 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
-	volatile immap_t *immap);
+	volatile cpm2_map_t *immap);
 
 #ifdef	CONFIG_USE_MDIO
 static int	mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
@@ -586,7 +586,7 @@ fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 	    }
 
 	    if (must_restart) {
-		volatile cpm8260_t *cp;
+		volatile cpm_cpm2_t *cp;
 
 		/* Some transmit errors cause the transmitter to shut
 		 * down.  We now issue a restart transmit.  Since the
@@ -1361,10 +1361,10 @@ static int __init fec_enet_init(void)
 	struct fcc_enet_private *cep;
 	fcc_info_t	*fip;
 	int	i, np, err;
-	volatile	immap_t		*immap;
-	volatile	iop8260_t	*io;
+	volatile	cpm2_map_t		*immap;
+	volatile	iop_cpm2_t	*io;
 
-	immap = (immap_t *)IMAP_ADDR;	/* and to internal registers */
+	immap = (cpm2_map_t *)CPM_MAP_ADDR;	/* and to internal registers */
 	io = &immap->im_ioport;
 
 	np = sizeof(fcc_ports) / sizeof(fcc_info_t);
@@ -1431,7 +1431,7 @@ module_init(fec_enet_init);
 */
 static void __init
 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
-						volatile immap_t *immap)
+						volatile cpm2_map_t *immap)
 {
 	volatile	fcc_enet_t	*ep;
 	volatile	fcc_t		*fccp;
@@ -1454,8 +1454,8 @@ init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
 /* Initialize the I/O pins for the FCC Ethernet.
 */
 static void __init
-init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
-						volatile immap_t *immap)
+init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
+						volatile cpm2_map_t *immap)
 {
 
 	/* FCC1 pins are on port A/C.  FCC2/3 are port B/C.
@@ -1513,7 +1513,7 @@ init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
 
 static void __init
 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
-						volatile immap_t *immap)
+						volatile cpm2_map_t *immap)
 {
 	unsigned char	*eap;
 	unsigned long	mem_addr;
@@ -1522,7 +1522,7 @@ init_fcc_param(fcc_info_t *fip, struct net_device *dev,
 	struct		fcc_enet_private *cep;
 	volatile	fcc_enet_t	*ep;
 	volatile	cbd_t		*bdp;
-	volatile	cpm8260_t	*cp;
+	volatile	cpm_cpm2_t	*cp;
 
 	cep = (struct fcc_enet_private *)(dev->priv);
 	ep = cep->ep;
@@ -1544,17 +1544,17 @@ init_fcc_param(fcc_info_t *fip, struct net_device *dev,
 	 * work with the data cache enabled, so I allocate from the
 	 * main memory instead.
 	 */
-	i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
+	i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
 	ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
 	cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
 
-	i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
+	i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
 	ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
 	cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
 #else
-	cep->rx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
+	cep->rx_bd_base = (cbd_t *)cpm2_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
 	ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
-	cep->tx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
+	cep->tx_bd_base = (cbd_t *)cpm2_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
 	ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
 #endif
 
@@ -1817,10 +1817,10 @@ mii_send_receive(fcc_info_t *fip, uint cmd)
 {
 	uint		retval;
 	int		read_op, i, off;
-	volatile	immap_t		*immap;
-	volatile	iop8260_t	*io;
+	volatile	cpm2_map_t		*immap;
+	volatile	iop_cpm2_t	*io;
 
-	immap = (immap_t *)IMAP_ADDR;
+	immap = (cpm2_map_t *)CPM_MAP_ADDR;
 	io = &immap->im_ioport;
 
 	io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);

arch/ppc/Kconfig

@@ -582,14 +582,23 @@ config EMBEDDEDBOOT
 	default y
 
 config 8260
-	bool "MPC8260 CPM Support" if WILLOW
+	bool "CPM2 Support" if WILLOW
 	depends on 6xx
 	default y if TQM8260 || RPXSUPER || EST8260 || SBS8260 || SBC82xx
 	help
-	  The MPC8260 CPM (Communications Processor Module) is a typical
-	  embedded CPU made by Motorola.  Selecting this option means that
-	  you wish to build a kernel for a machine with specifically an 8260
-	  for a CPU.
+	  The MPC8260 is a typical embedded CPU made by Motorola.  Selecting
+	  this option means that you wish to build a kernel for a machine with
+	  an 8260 class CPU.
+
+config CPM2
+	bool
+	depends on 8260
+	default y
+	help
+	  The CPM2 (Communications Processor Module) is a coprocessor on
+	  embedded CPUs made by Motorola.  Selecting this option means that
+	  you wish to build a kernel for a machine with a CPM2 coprocessor
+	  on it (826x, 827x, 8560).
 
 config PPC_CHRP
 	bool
@@ -672,11 +681,11 @@ config SPRUCE_BAUD_33M
 
 config PC_KEYBOARD
 	bool "PC PS/2 style Keyboard"
-	depends on 4xx || 8260
+	depends on 4xx || CPM2
 
 config SERIAL_CONSOLE
 	bool
-	depends on 8xx || 8260
+	depends on 8xx || CPM2
 	default y
 
 config SERIAL_CONSOLE_BAUD
@@ -957,7 +966,7 @@ config ISA
 
 config GENERIC_ISA_DMA
 	bool
-	depends on POWER3 || POWER4 || 6xx && !8260
+	depends on POWER3 || POWER4 || 6xx && !CPM2
 	default y
 
 config EISA
@@ -974,10 +983,10 @@ config MCA
 	bool
 
 config PCI
-	bool "PCI support" if 40x || 8260
-	default y if !40x && !8260 && !8xx && !APUS
-	default PCI_PERMEDIA if !4xx && !8260 && !8xx && APUS
-	default PCI_QSPAN if !4xx && !8260 && 8xx
+	bool "PCI support" if 40x || CPM2
+	default y if !40x && !CPM2 && !8xx && !APUS
+	default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
+	default PCI_QSPAN if !4xx && !CPM2 && 8xx
 	help
 	  Find out whether your system includes a PCI bus. PCI is the name of
 	  a bus system, i.e. the way the CPU talks to the other stuff inside
@@ -990,7 +999,7 @@ config PCI_DOMAINS
 
 config PCI_QSPAN
 	bool "QSpan PCI"
-	depends on !4xx && !8260 && 8xx
+	depends on !4xx && !CPM2 && 8xx
 	help
 	  Say Y here if you have a system based on a Motorola 8xx-series
 	  embedded processor with a QSPAN PCI interface, otherwise say N.
@@ -1229,7 +1238,7 @@ endchoice
 
 config KGDB_CONSOLE
 	bool "Enable serial console thru kgdb port"
-	depends on KGDB && 8xx || 8260
+	depends on KGDB && 8xx || CPM2
 	help
 	  If you enable this, all serial console messages will be sent
 	  over the gdb stub.

arch/ppc/Makefile

@@ -42,7 +42,7 @@ core-$(CONFIG_XMON)		+= arch/ppc/xmon/
 core-$(CONFIG_APUS)		+= arch/ppc/amiga/
 drivers-$(CONFIG_8xx)		+= arch/ppc/8xx_io/
 drivers-$(CONFIG_4xx)		+= arch/ppc/4xx_io/
-drivers-$(CONFIG_8260)		+= arch/ppc/8260_io/
+drivers-$(CONFIG_CPM2)		+= arch/ppc/8260_io/
 
 BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd vmlinux.sm
 

arch/ppc/boot/simple/embed_config.c

@@ -16,7 +16,7 @@
 #endif
 #ifdef CONFIG_8260
 #include <asm/mpc8260.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #endif
 #ifdef CONFIG_40x
 #include <asm/io.h>
@@ -415,9 +415,9 @@ clk_8260(bd_t *bd)
 {
 	uint	scmr, vco_out, clkin;
 	uint	plldf, pllmf, corecnf;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 	scmr = ip->im_clkrst.car_scmr;
 
 	/* The clkin is always bus frequency.
@@ -457,9 +457,9 @@ clk_8280(bd_t *bd)
 {
 	uint	scmr, main_clk, clkin;
 	uint	pllmf, corecnf;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 	scmr = ip->im_clkrst.car_scmr;
 
 	/* The clkin is always bus frequency.

arch/ppc/boot/simple/m8260_tty.c

@@ -3,7 +3,8 @@
  */
 #include <linux/types.h>
 #include <asm/mpc8260.h>
-#include <asm/cpm_8260.h>
+#include <asm/cpm2.h>
+#include <asm/immap_cpm2.h>
 
 uint	no_print;
 extern char	*params[];
@@ -29,12 +30,12 @@ serial_init(int ignored, bd_t *bd)
 	volatile scc_uart_t	*sup;
 #endif
 	volatile cbd_t	*tbdf, *rbdf;
-	volatile immap_t	*ip;
-	volatile iop8260_t	*io;
-	volatile cpm8260_t	*cp;
+	volatile cpm2_map_t	*ip;
+	volatile iop_cpm2_t	*io;
+	volatile cpm_cpm2_t	*cp;
 	uint	dpaddr, memaddr;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 	cp = &ip->im_cpm;
 	io = &ip->im_ioport;
 
@@ -223,10 +224,10 @@ serial_readbuf(u_char *cbuf)
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
 	volatile scc_uart_t	*sup;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 	int	i, nc;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 
 #ifdef SCC_CONSOLE
 	sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
@@ -255,10 +256,10 @@ serial_putc(void *ignored, const char c)
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
 	volatile scc_uart_t	*sup;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 	extern bd_t		*board_info;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 #ifdef SCC_CONSOLE
 	sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
 	tbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_tbase];
@@ -298,9 +299,9 @@ serial_tstc(void *ignored)
 	volatile cbd_t		*rbdf;
 	volatile smc_uart_t	*up;
 	volatile scc_uart_t	*sup;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 #ifdef SCC_CONSOLE
 	sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
 	rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];

arch/ppc/platforms/est8260.h

@@ -6,7 +6,7 @@
 #ifndef __EST8260_PLATFORM
 #define __EST8260_PLATFORM
 
-#define IMAP_ADDR		((uint)0xf0000000)
+#define CPM_MAP_ADDR		((uint)0xf0000000)
 
 #define BOOTROM_RESTART_ADDR	((uint)0xff000104)
 

arch/ppc/platforms/rpxsuper.h

@@ -32,7 +32,7 @@ extern bd_t m8xx_board_info;
  * We just map a few things we need.  The CSR is actually 4 byte-wide
  * registers that can be accessed as 8-, 16-, or 32-bit values.
  */
-#define IMAP_ADDR		((uint)0xf0000000)
+#define CPM_MAP_ADDR		((uint)0xf0000000)
 #define RPX_CSR_ADDR		((uint)0xfa000000)
 #define RPX_CSR_SIZE		((uint)(512 * 1024))
 #define RPX_NVRTC_ADDR		((uint)0xfa080000)

arch/ppc/platforms/sbc82xx.c

@@ -23,7 +23,7 @@
 #include <asm/machdep.h>
 #include <asm/io.h>
 #include <asm/todc.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 
 static void (*callback_setup_arch)(void);
 
@@ -67,7 +67,7 @@ TODC_ALLOC();
 #ifdef CONFIG_GEN_RTC
 static void sbc82xx_time_init(void)
 {
-	volatile memctl8260_t *mc = &immr->im_memctl;
+	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
 	TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
 
 	/* Set up CS11 for RTC chip */

arch/ppc/platforms/sbc82xx.h

@@ -9,7 +9,6 @@
 
 #include <asm/ppcboot.h>
 
-#define IMAP_ADDR			0xf0000000
 #define CPM_MAP_ADDR			0xf0000000
 
 #define SBC82xx_TODC_NVRAM_ADDR		0x80000000

arch/ppc/platforms/sbs8260.h

@@ -5,7 +5,7 @@
  * the configuration SCMR and the Power-On-Reset word.
  */
 
-#define IMAP_ADDR	((uint)0xfe000000)
+#define CPM_MAP_ADDR	((uint)0xfe000000)
 
 
 /* A Board Information structure that is given to a program when

arch/ppc/platforms/tqm8260.h

@@ -11,7 +11,7 @@
 
 #include <asm/ppcboot.h>
 
-#define IMAP_ADDR		((uint)0xFFF00000)
+#define CPM_MAP_ADDR		((uint)0xFFF00000)
 #define PHY_INTERRUPT		25
 
 #define BOOTROM_RESTART_ADDR	((uint)0x40000104)

arch/ppc/platforms/tqm8260_setup.c

@@ -17,7 +17,7 @@
 #include <linux/config.h>
 #include <linux/seq_file.h>
 
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/mpc8260.h>
 #include <asm/machdep.h>
 
@@ -44,8 +44,8 @@ tqm8260_show_cpuinfo(struct seq_file *m)
 static int
 tqm8260_set_rtc_time(unsigned long time)
 {
-	((immap_t *)IMAP_ADDR)->im_sit.sit_tmcnt = time;
-	((immap_t *)IMAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
+	((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt = time;
+	((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
 
 	return(0);
 }
@@ -53,7 +53,7 @@ tqm8260_set_rtc_time(unsigned long time)
 static unsigned long
 tqm8260_get_rtc_time(void)
 {
-	return ((immap_t *)IMAP_ADDR)->im_sit.sit_tmcnt;
+	return ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt;
 }
 
 static void __init

arch/ppc/syslib/Makefile

@@ -66,7 +66,7 @@ obj-$(CONFIG_SANDPOINT)		+= i8259.o open_pic.o pci_auto.o todc_time.o
 obj-$(CONFIG_SBC82xx)		+= todc_time.o
 obj-$(CONFIG_SPRUCE)		+= cpc700_pic.o indirect_pci.o pci_auto.o \
 				   todc_time.o
-obj-$(CONFIG_8260)		+= m8260_setup.o ppc8260_pic.o
+obj-$(CONFIG_8260)		+= m8260_setup.o cpm2_pic.o
 ifeq ($(CONFIG_PPC_GEN550),y)
 obj-$(CONFIG_KGDB)		+= gen550_kgdb.o gen550_dbg.o
 obj-$(CONFIG_SERIAL_TEXT_DEBUG)	+= gen550_dbg.o

arch/ppc/syslib/ppc8260_pic.c → arch/ppc/syslib/cpm2_pic.c

@@ -3,11 +3,11 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <asm/irq.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/mpc8260.h>
-#include "ppc8260_pic.h"
+#include "cpm2_pic.h"
 
-/* The 8260 internal interrupt controller.  It is usually
+/* The CPM2 internal interrupt controller.  It is usually
  * the only interrupt controller.
  * There are two 32-bit registers (high/low) for up to 64
  * possible interrupts.
@@ -40,7 +40,7 @@ static	u_char	irq_to_siubit[] = {
 	 7,  6,  5,  4,  3,  2,  1,  0
 };
 
-static void m8260_mask_irq(unsigned int irq_nr)
+static void cpm2_mask_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -48,12 +48,12 @@ static void m8260_mask_irq(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(immr->im_intctl.ic_simrh);
+	simr = &(cpm2_immr->im_intctl.ic_simrh);
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 }
 
-static void m8260_unmask_irq(unsigned int irq_nr)
+static void cpm2_unmask_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -61,12 +61,12 @@ static void m8260_unmask_irq(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(immr->im_intctl.ic_simrh);
+	simr = &(cpm2_immr->im_intctl.ic_simrh);
 	ppc_cached_irq_mask[word] |= (1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 }
 
-static void m8260_mask_and_ack(unsigned int irq_nr)
+static void cpm2_mask_and_ack(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr, *sipnr;
@@ -74,14 +74,14 @@ static void m8260_mask_and_ack(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(immr->im_intctl.ic_simrh);
-	sipnr = &(immr->im_intctl.ic_sipnrh);
+	simr = &(cpm2_immr->im_intctl.ic_simrh);
+	sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 	sipnr[word] = 1 << (31 - bit);
 }
 
-static void m8260_end_irq(unsigned int irq_nr)
+static void cpm2_end_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -92,33 +92,33 @@ static void m8260_end_irq(unsigned int irq_nr)
 		bit = irq_to_siubit[irq_nr];
 		word = irq_to_siureg[irq_nr];
 
-		simr = &(immr->im_intctl.ic_simrh);
+		simr = &(cpm2_immr->im_intctl.ic_simrh);
 		ppc_cached_irq_mask[word] |= (1 << (31 - bit));
 		simr[word] = ppc_cached_irq_mask[word];
 	}
 }
 
-struct hw_interrupt_type ppc8260_pic = {
-	" 8260 SIU  ",
+struct hw_interrupt_type cpm2_pic = {
+	" CPM2 SIU  ",
 	NULL,
 	NULL,
-	m8260_unmask_irq,
-	m8260_mask_irq,
-	m8260_mask_and_ack,
-	m8260_end_irq,
+	cpm2_unmask_irq,
+	cpm2_mask_irq,
+	cpm2_mask_and_ack,
+	cpm2_end_irq,
 	0
 };
 
 
 int
-m8260_get_irq(struct pt_regs *regs)
+cpm2_get_irq(struct pt_regs *regs)
 {
 	int irq;
         unsigned long bits;
 
-        /* For MPC8260, read the SIVEC register and shift the bits down
+        /* For CPM2, read the SIVEC register and shift the bits down
          * to get the irq number.         */
-        bits = immr->im_intctl.ic_sivec;
+        bits = cpm2_immr->im_intctl.ic_sivec;
         irq = bits >> 26;
 
 	if (irq == 0)

arch/ppc/syslib/cpm2_pic.h

+#ifndef _PPC_KERNEL_CPM2_H
+#define _PPC_KERNEL_CPM2_H
+
+#include <linux/irq.h>
+
+extern struct hw_interrupt_type cpm2_pic;
+
+void cpm2_pic_init(void);
+void cpm2_do_IRQ(struct pt_regs *regs,
+                 int            cpu);
+int cpm2_get_irq(struct pt_regs *regs);
+
+#endif /* _PPC_KERNEL_CPM2_H */

arch/ppc/syslib/m8260_setup.c

@@ -39,12 +39,12 @@
 #include <asm/pgtable.h>
 #include <asm/ide.h>
 #include <asm/mpc8260.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/machdep.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 
-#include "ppc8260_pic.h"
+#include "cpm2_pic.h"
 
 static int m8260_set_rtc_time(unsigned long time);
 static unsigned long m8260_get_rtc_time(void);
@@ -52,14 +52,14 @@ static void m8260_calibrate_decr(void);
 
 unsigned char __res[sizeof(bd_t)];
 
-extern void m8260_cpm_reset(void);
+extern void cpm2_reset(void);
 
 static void __init
 m8260_setup_arch(void)
 {
 	/* Reset the Communication Processor Module.
 	*/
-	m8260_cpm_reset();
+	cpm2_reset();
 }
 
 /* The decrementer counts at the system (internal) clock frequency
@@ -142,9 +142,9 @@ m8260_show_percpuinfo(struct seq_file *m, int i)
 
 	bp = (bd_t *)__res;
 
-	seq_printf(m, "core clock\t: %d MHz\n"
-		   "CPM  clock\t: %d MHz\n"
-		   "bus  clock\t: %d MHz\n",
+	seq_printf(m, "core clock\t: %ld MHz\n"
+		   "CPM  clock\t: %ld MHz\n"
+		   "bus  clock\t: %ld MHz\n",
 		   bp->bi_intfreq / 1000000,
 		   bp->bi_cpmfreq / 1000000,
 		   bp->bi_busfreq / 1000000);
@@ -164,15 +164,15 @@ m8260_init_IRQ(void)
 	void cpm_interrupt_init(void);
 
         for ( i = 0 ; i < NR_SIU_INTS ; i++ )
-                irq_desc[i].handler = &ppc8260_pic;
+                irq_desc[i].handler = &cpm2_pic;
 
 	/* Initialize the default interrupt mapping priorities,
 	 * in case the boot rom changed something on us.
 	 */
-	immr->im_intctl.ic_sicr = 0;
-	immr->im_intctl.ic_siprr = 0x05309770;
-	immr->im_intctl.ic_scprrh = 0x05309770;
-	immr->im_intctl.ic_scprrl = 0x05309770;
+	cpm2_immr->im_intctl.ic_sicr = 0;
+	cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+	cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
+	cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
 }
 
 /*
@@ -200,7 +200,7 @@ m8260_map_io(void)
 	uint addr;
 
 	/* Map IMMR region to a 256MB BAT */
-	addr = (immr != NULL) ? (uint)immr : IMAP_ADDR;
+	addr = (cpm2_immr != NULL) ? (uint)cpm2_immr : CPM_MAP_ADDR;
 	io_block_mapping(addr, addr, 0x10000000, _PAGE_IO);
 
 	/* Map I/O region to a 256MB BAT */
@@ -244,7 +244,7 @@ m8260_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	ppc_md.show_percpuinfo		= m8260_show_percpuinfo;
 	ppc_md.irq_canonicalize	= NULL;
 	ppc_md.init_IRQ			= m8260_init_IRQ;
-	ppc_md.get_irq			= m8260_get_irq;
+	ppc_md.get_irq			= cpm2_get_irq;
 	ppc_md.init			= NULL;
 
 	ppc_md.restart			= m8260_restart;

arch/ppc/syslib/ppc8260_pic.h

-#ifndef _PPC_KERNEL_PPC8260_H
-#define _PPC_KERNEL_PPC8260_H
-
-#include <linux/irq.h>
-
-extern struct hw_interrupt_type ppc8260_pic;
-
-void m8260_pic_init(void);
-void m8260_do_IRQ(struct pt_regs *regs,
-                 int            cpu);
-int m8260_get_irq(struct pt_regs *regs);
-
-#endif /* _PPC_KERNEL_PPC8260_H */

drivers/mtd/maps/wr_sbc82xx_flash.c

@@ -20,7 +20,7 @@
 #include <linux/config.h>
 #include <linux/mtd/partitions.h>
 
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 
 static struct mtd_info *sbcmtd[3];
 static struct mtd_partition *sbcmtd_parts[3];
@@ -59,7 +59,7 @@ static const char *part_probes[] __initdata = {"cmdlinepart", "RedBoot", NULL};
 
 int __init init_sbc82xx_flash(void)
 {
-	volatile  memctl8260_t *mc = &immr->im_memctl;
+	volatile  memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
 	int bigflash;
 	int i;
 

include/asm-ppc/immap_8260.h

-/*
- * MPC8260 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * The Internal Memory Map of the 8260.  I don't know how generic
- * this will be, as I don't have any knowledge of the subsequent
- * parts at this time.  I copied this from the 8xx_immap.h.
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_82XX__
-#define __IMMAP_82XX__
-
-/* System configuration registers.
-*/
-typedef	struct sys_conf {
-	uint	sc_siumcr;
-	uint	sc_sypcr;
-	char	res1[6];
-	ushort	sc_swsr;
-	char	res2[20];
-	uint	sc_bcr;
-	u_char	sc_ppc_acr;
-	char	res3[3];
-	uint	sc_ppc_alrh;
-	uint	sc_ppc_alrl;
-	u_char	sc_lcl_acr;
-	char	res4[3];
-	uint	sc_lcl_alrh;
-	uint	sc_lcl_alrl;
-	uint	sc_tescr1;
-	uint	sc_tescr2;
-	uint	sc_ltescr1;
-	uint	sc_ltescr2;
-	uint	sc_pdtea;
-	u_char	sc_pdtem;
-	char	res5[3];
-	uint	sc_ldtea;
-	u_char	sc_ldtem;
-	char	res6[163];
-} sysconf8260_t;
-
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	uint	memc_br0;
-	uint	memc_or0;
-	uint	memc_br1;
-	uint	memc_or1;
-	uint	memc_br2;
-	uint	memc_or2;
-	uint	memc_br3;
-	uint	memc_or3;
-	uint	memc_br4;
-	uint	memc_or4;
-	uint	memc_br5;
-	uint	memc_or5;
-	uint	memc_br6;
-	uint	memc_or6;
-	uint	memc_br7;
-	uint	memc_or7;
-	uint	memc_br8;
-	uint	memc_or8;
-	uint	memc_br9;
-	uint	memc_or9;
-	uint	memc_br10;
-	uint	memc_or10;
-	uint	memc_br11;
-	uint	memc_or11;
-	char	res1[8];
-	uint	memc_mar;
-	char	res2[4];
-	uint	memc_mamr;
-	uint	memc_mbmr;
-	uint	memc_mcmr;
-	char	res3[8];
-	ushort	memc_mptpr;
-	char	res4[2];
-	uint	memc_mdr;
-	char	res5[4];
-	uint	memc_psdmr;
-	uint	memc_lsdmr;
-	u_char	memc_purt;
-	char	res6[3];
-	u_char	memc_psrt;
-	char	res7[3];
-	u_char	memc_lurt;
-	char	res8[3];
-	u_char	memc_lsrt;
-	char	res9[3];
-	uint	memc_immr;
-	char	res10[84];
-} memctl8260_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	char	res1[32];
-	ushort	sit_tmcntsc;
-	char	res2[2];
-	uint	sit_tmcnt;
-	char	res3[4];
-	uint	sit_tmcntal;
-	char	res4[16];
-	ushort	sit_piscr;
-	char	res5[2];
-	uint	sit_pitc;
-	uint	sit_pitr;
-	char	res6[94];
-	char	res7[2390];
-} sit8260_t;
-
-#define PISCR_PIRQ_MASK		((ushort)0xff00)
-#define PISCR_PS		((ushort)0x0080)
-#define PISCR_PIE		((ushort)0x0004)
-#define PISCR_PTF		((ushort)0x0002)
-#define PISCR_PTE		((ushort)0x0001)
-
-/* Interrupt Controller.
-*/
-typedef struct interrupt_controller {
-	ushort	ic_sicr;
-	char	res1[2];
-	uint	ic_sivec;
-	uint	ic_sipnrh;
-	uint	ic_sipnrl;
-	uint	ic_siprr;
-	uint	ic_scprrh;
-	uint	ic_scprrl;
-	uint	ic_simrh;
-	uint	ic_simrl;
-	uint	ic_siexr;
-	char	res2[88];
-} intctl8260_t;
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	uint	car_sccr;
-	char	res1[4];
-	uint	car_scmr;
-	char	res2[4];
-	uint	car_rsr;
-	uint	car_rmr;
-	char	res[104];
-} car8260_t;
-
-/* Input/Output Port control/status registers.
- * Names consistent with processor manual, although they are different
- * from the original 8xx names.......
- */
-typedef struct io_port {
-	uint	iop_pdira;
-	uint	iop_ppara;
-	uint	iop_psora;
-	uint	iop_podra;
-	uint	iop_pdata;
-	char	res1[12];
-	uint	iop_pdirb;
-	uint	iop_pparb;
-	uint	iop_psorb;
-	uint	iop_podrb;
-	uint	iop_pdatb;
-	char	res2[12];
-	uint	iop_pdirc;
-	uint	iop_pparc;
-	uint	iop_psorc;
-	uint	iop_podrc;
-	uint	iop_pdatc;
-	char	res3[12];
-	uint	iop_pdird;
-	uint	iop_ppard;
-	uint	iop_psord;
-	uint	iop_podrd;
-	uint	iop_pdatd;
-	char	res4[12];
-} iop8260_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	u_char	cpmt_tgcr1;
-	char	res1[3];
-	u_char	cpmt_tgcr2;
-	char	res2[11];
-	ushort	cpmt_tmr1;
-	ushort	cpmt_tmr2;
-	ushort	cpmt_trr1;
-	ushort	cpmt_trr2;
-	ushort	cpmt_tcr1;
-	ushort	cpmt_tcr2;
-	ushort	cpmt_tcn1;
-	ushort	cpmt_tcn2;
-	ushort	cpmt_tmr3;
-	ushort	cpmt_tmr4;
-	ushort	cpmt_trr3;
-	ushort	cpmt_trr4;
-	ushort	cpmt_tcr3;
-	ushort	cpmt_tcr4;
-	ushort	cpmt_tcn3;
-	ushort	cpmt_tcn4;
-	ushort	cpmt_ter1;
-	ushort	cpmt_ter2;
-	ushort	cpmt_ter3;
-	ushort	cpmt_ter4;
-	char	res3[584];
-} cpmtimer8260_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	char	res0[24];
-	u_char	sdma_sdsr;
-	char	res1[3];
-	u_char	sdma_sdmr;
-	char	res2[3];
-	u_char	sdma_idsr1;
-	char	res3[3];
-	u_char	sdma_idmr1;
-	char	res4[3];
-	u_char	sdma_idsr2;
-	char	res5[3];
-	u_char	sdma_idmr2;
-	char	res6[3];
-	u_char	sdma_idsr3;
-	char	res7[3];
-	u_char	sdma_idmr3;
-	char	res8[3];
-	u_char	sdma_idsr4;
-	char	res9[3];
-	u_char	sdma_idmr4;
-	char	res10[707];
-} sdma8260_t;
-
-/* Fast controllers
-*/
-typedef struct fcc {
-	uint	fcc_gfmr;
-	uint	fcc_fpsmr;
-	ushort	fcc_ftodr;
-	char	res1[2];
-	ushort	fcc_fdsr;
-	char	res2[2];
-	ushort	fcc_fcce;
-	char	res3[2];
-	ushort	fcc_fccm;
-	char	res4[2];
-	u_char	fcc_fccs;
-	char	res5[3];
-	u_char	fcc_ftirr_phy[4];
-} fcc_t;
-
-/* I2C
-*/
-typedef struct i2c {
-	u_char	i2c_i2mod;
-	char	res1[3];
-	u_char	i2c_i2add;
-	char	res2[3];
-	u_char	i2c_i2brg;
-	char	res3[3];
-	u_char	i2c_i2com;
-	char	res4[3];
-	u_char	i2c_i2cer;
-	char	res5[3];
-	u_char	i2c_i2cmr;
-	char	res6[331];
-} i2c8260_t;
-
-typedef struct scc {		/* Serial communication channels */
-	uint	scc_gsmrl;
-	uint	scc_gsmrh;
-	ushort	scc_pmsr;
-	char	res1[2];
-	ushort	scc_todr;
-	ushort	scc_dsr;
-	ushort	scc_scce;
-	char	res2[2];
-	ushort	scc_sccm;
-	char	res3;
-	u_char	scc_sccs;
-	char	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	char	res1[2];
-	ushort	smc_smcmr;
-	char	res2[2];
-	u_char	smc_smce;
-	char	res3[3];
-	u_char	smc_smcm;
-	char	res4[5];
-} smc_t;
-
-/* Serial Peripheral Interface.
-*/
-typedef struct spi {
-	ushort	spi_spmode;
-	char	res1[4];
-	u_char	spi_spie;
-	char	res2[3];
-	u_char	spi_spim;
-	char	res3[2];
-	u_char	spi_spcom;
-	char	res4[82];
-} spi_t;
-
-/* CPM Mux.
-*/
-typedef struct cpmux {
-	u_char	cmx_si1cr;
-	char	res1;
-	u_char	cmx_si2cr;
-	char	res2;
-	uint	cmx_fcr;
-	uint	cmx_scr;
-	u_char	cmx_smr;
-	char	res3;
-	ushort	cmx_uar;
-	char	res4[16];
-} cpmux_t;
-
-/* SIRAM control
-*/
-typedef struct siram {
-	ushort	si_amr;
-	ushort	si_bmr;
-	ushort	si_cmr;
-	ushort	si_dmr;
-	u_char	si_gmr;
-	char	res1;
-	u_char	si_cmdr;
-	char	res2;
-	u_char	si_str;
-	char	res3;
-	ushort	si_rsr;
-} siramctl_t;
-
-typedef struct mcc {
-	ushort	mcc_mcce;
-	char	res1[2];
-	ushort	mcc_mccm;
-	char	res2[2];
-	u_char	mcc_mccf;
-	char	res3[7];
-} mcc_t;
-
-typedef struct comm_proc {
-	uint	cp_cpcr;
-	uint	cp_rccr;
-	char	res1[14];
-	ushort	cp_rter;
-	char	res2[2];
-	ushort	cp_rtmr;
-	ushort	cp_rtscr;
-	char	res3[2];
-	uint	cp_rtsr;
-	char	res4[12];
-} cpm8260_t;
-
-/* ...and the whole thing wrapped up....
-*/
-typedef struct immap {
-	/* Some references are into the unique and known dpram spaces,
-	 * others are from the generic base.
-	 */
-#define im_dprambase	im_dpram1
-	u_char		im_dpram1[16*1024];
-	char		res1[16*1024];
-	u_char		im_dpram2[4*1024];
-	char		res2[8*1024];
-	u_char		im_dpram3[4*1024];
-	char		res3[16*1024];
-
-	sysconf8260_t	im_siu_conf;	/* SIU Configuration */
-	memctl8260_t	im_memctl;	/* Memory Controller */
-	sit8260_t	im_sit;		/* System Integration Timers */
-	intctl8260_t	im_intctl;	/* Interrupt Controller */
-	car8260_t	im_clkrst;	/* Clocks and reset */
-	iop8260_t	im_ioport;	/* IO Port control/status */
-	cpmtimer8260_t	im_cpmtimer;	/* CPM timers */
-	sdma8260_t	im_sdma;	/* SDMA control/status */
-
-	fcc_t		im_fcc[3];	/* Three FCCs */
-
-	char		res4[159];
-
-	/* First set of baud rate generators.
-	*/
-	char		res4a[496];
-	uint		im_brgc5;
-	uint		im_brgc6;
-	uint		im_brgc7;
-	uint		im_brgc8;
-
-	char		res5[608];
-
-	i2c8260_t	im_i2c;		/* I2C control/status */
-	cpm8260_t	im_cpm;		/* Communication processor */
-
-	/* Second set of baud rate generators.
-	*/
-	uint		im_brgc1;
-	uint		im_brgc2;
-	uint		im_brgc3;
-	uint		im_brgc4;
-
-	scc_t		im_scc[4];	/* Four SCCs */
-	smc_t		im_smc[2];	/* Couple of SMCs */
-	spi_t		im_spi;		/* A SPI */
-	cpmux_t		im_cpmux;	/* CPM clock route mux */
-	siramctl_t	im_siramctl1;	/* First SI RAM Control */
-	mcc_t		im_mcc1;	/* First MCC */
-	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
-	mcc_t		im_mcc2;	/* Second MCC */
-
-	char		res6[1184];
-
-	ushort		im_si1txram[256];
-	char		res7[512];
-	ushort		im_si1rxram[256];
-	char		res8[512];
-	ushort		im_si2txram[256];
-	char		res9[512];
-	ushort		im_si2rxram[256];
-	char		res10[512];
-	char		res11[4096];
-} immap_t;
-
-extern immap_t	*immr;
-
-#endif /* __IMMAP_82XX__ */
-#endif /* __KERNEL__ */

include/asm-ppc/irq.h

@@ -177,17 +177,55 @@ static __inline__ int irq_canonicalize(int irq)
  */
 #define NR_SIU_INTS	64
 
-/* There are many more than these, we will add them as we need them.
-*/
+#define	SIU_INT_ERROR		((uint)0x00)
+#define	SIU_INT_I2C		((uint)0x01)
+#define	SIU_INT_SPI		((uint)0x02)
+#define	SIU_INT_RISC		((uint)0x03)
 #define	SIU_INT_SMC1		((uint)0x04)
 #define	SIU_INT_SMC2		((uint)0x05)
+#define	SIU_INT_IDMA1		((uint)0x06)
+#define	SIU_INT_IDMA2		((uint)0x07)
+#define	SIU_INT_IDMA3		((uint)0x08)
+#define	SIU_INT_IDMA4		((uint)0x09)
+#define	SIU_INT_SDMA		((uint)0x0a)
+#define	SIU_INT_TIMER1		((uint)0x0c)
+#define	SIU_INT_TIMER2		((uint)0x0d)
+#define	SIU_INT_TIMER3		((uint)0x0e)
+#define	SIU_INT_TIMER4		((uint)0x0f)
+#define	SIU_INT_TMCNT		((uint)0x10)
+#define	SIU_INT_PIT		((uint)0x11)
+#define	SIU_INT_IRQ1		((uint)0x13)
+#define	SIU_INT_IRQ2		((uint)0x14)
+#define	SIU_INT_IRQ3		((uint)0x15)
+#define	SIU_INT_IRQ4		((uint)0x16)
+#define	SIU_INT_IRQ5		((uint)0x17)
+#define	SIU_INT_IRQ6		((uint)0x18)
+#define	SIU_INT_IRQ7		((uint)0x19)
 #define	SIU_INT_FCC1		((uint)0x20)
 #define	SIU_INT_FCC2		((uint)0x21)
 #define	SIU_INT_FCC3		((uint)0x22)
+#define	SIU_INT_MCC1		((uint)0x24)
+#define	SIU_INT_MCC2		((uint)0x25)
 #define	SIU_INT_SCC1		((uint)0x28)
 #define	SIU_INT_SCC2		((uint)0x29)
 #define	SIU_INT_SCC3		((uint)0x2a)
 #define	SIU_INT_SCC4		((uint)0x2b)
+#define	SIU_INT_PC15		((uint)0x30)
+#define	SIU_INT_PC14		((uint)0x31)
+#define	SIU_INT_PC13		((uint)0x32)
+#define	SIU_INT_PC12		((uint)0x33)
+#define	SIU_INT_PC11		((uint)0x34)
+#define	SIU_INT_PC10		((uint)0x35)
+#define	SIU_INT_PC9		((uint)0x36)
+#define	SIU_INT_PC8		((uint)0x37)
+#define	SIU_INT_PC7		((uint)0x38)
+#define	SIU_INT_PC6		((uint)0x39)
+#define	SIU_INT_PC5		((uint)0x3a)
+#define	SIU_INT_PC4		((uint)0x3b)
+#define	SIU_INT_PC3		((uint)0x3c)
+#define	SIU_INT_PC2		((uint)0x3d)
+#define	SIU_INT_PC1		((uint)0x3e)
+#define	SIU_INT_PC0		((uint)0x3f)
 
 #endif /* CONFIG_8260 */
 

include/asm-ppc/ppcboot.h

@@ -52,7 +52,7 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_CPM2)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
@@ -61,7 +61,7 @@ typedef struct bd_info {
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_CPM2)
 	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
 	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
 	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */