Commit e02d026f authored by Rikard Falkeborn's avatar Rikard Falkeborn Committed by Paul Burton

MIPS: Loongson: Fix GENMASK misuse

Arguments are supposed to be ordered high then low.

Fixes: 6a6f9b7d ("MIPS: Loongson: Add CFUCFG&CSR support")
Signed-off-by: default avatarRikard Falkeborn <rikard.falkeborn@gmail.com>
Reviewed-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarPaul Burton <paulburton@kernel.org>
Cc: chenhuacai@gmail.com
Cc: jhogan@kernel.org
Cc: jiaxun.yang@flygoat.com
Cc: linux-mips@linux-mips.org
Cc: linux-mips@vger.kernel.org
Cc: paul.burton@mips.com
Cc: ralf@linux-mips.org
Cc: wuzhangjin@gmail.com
Cc: zhangfx@lemote.com
parent 9dd422f6
...@@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg) ...@@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg)
#define LOONGSON_CFG2_LGFTP BIT(19) #define LOONGSON_CFG2_LGFTP BIT(19)
#define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20)
#define LOONGSON_CFG2_LLFTP BIT(23) #define LOONGSON_CFG2_LLFTP BIT(23)
#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26) #define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24)
#define LOONGSON_CFG2_LCSRP BIT(27) #define LOONGSON_CFG2_LCSRP BIT(27)
#define LOONGSON_CFG2_LDISBLIKELY BIT(28) #define LOONGSON_CFG2_LDISBLIKELY BIT(28)
......
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