Commit e08b3c8b authored by Jayamohan Kallickal's avatar Jayamohan Kallickal Committed by James Bottomley

[SCSI] be2iscsi: Fix doorbell format for EQ/CQ/RQ s per SLI spec.

The doorbel format has been updated to support additonal functionalities
of SKH-R adapter. These changes are made such that older FW also works fine.
Signed-off-by: default avatarJohn Soni Jose <sony.john-n@emulex.com>
Signed-off-by: default avatarJayamohan Kallickal <jayamohan.kallickal@emulex.com>
Reviewed-by: default avatarMike Christie <michaelc@cs.wisc.edu>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 3e393172
...@@ -432,18 +432,6 @@ void beiscsi_async_link_state_process(struct beiscsi_hba *phba, ...@@ -432,18 +432,6 @@ void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
} }
} }
static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm,
u16 num_popped)
{
u32 val = 0;
val |= qid & DB_CQ_RING_ID_MASK;
if (arm)
val |= 1 << DB_CQ_REARM_SHIFT;
val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
iowrite32(val, phba->db_va + DB_CQ_OFFSET);
}
int beiscsi_process_mcc(struct beiscsi_hba *phba) int beiscsi_process_mcc(struct beiscsi_hba *phba)
{ {
struct be_mcc_compl *compl; struct be_mcc_compl *compl;
...@@ -474,7 +462,7 @@ int beiscsi_process_mcc(struct beiscsi_hba *phba) ...@@ -474,7 +462,7 @@ int beiscsi_process_mcc(struct beiscsi_hba *phba)
} }
if (num) if (num)
beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num); hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1, 0);
spin_unlock_bh(&phba->ctrl.mcc_cq_lock); spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
return status; return status;
......
...@@ -103,7 +103,7 @@ struct be_mcc_compl { ...@@ -103,7 +103,7 @@ struct be_mcc_compl {
/********** MCC door bell ************/ /********** MCC door bell ************/
#define DB_MCCQ_OFFSET 0x140 #define DB_MCCQ_OFFSET 0x140
#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ #define DB_MCCQ_RING_ID_MASK 0xFFFF /* bits 0 - 15 */
/* Number of entries posted */ /* Number of entries posted */
#define DB_MCCQ_NUM_POSTED_SHIFT 16 /* bits 16 - 29 */ #define DB_MCCQ_NUM_POSTED_SHIFT 16 /* bits 16 - 29 */
...@@ -1018,8 +1018,8 @@ struct be_mcc_wrb_context { ...@@ -1018,8 +1018,8 @@ struct be_mcc_wrb_context {
int *users_final_status; int *users_final_status;
} __packed; } __packed;
#define DB_DEF_PDU_RING_ID_MASK 0x3FF /* bits 0 - 9 */ #define DB_DEF_PDU_RING_ID_MASK 0x3FFF /* bits 0 - 13 */
#define DB_DEF_PDU_CQPROC_MASK 0x3FFF /* bits 0 - 9 */ #define DB_DEF_PDU_CQPROC_MASK 0x3FFF /* bits 16 - 29 */
#define DB_DEF_PDU_REARM_SHIFT 14 #define DB_DEF_PDU_REARM_SHIFT 14
#define DB_DEF_PDU_EVENT_SHIFT 15 #define DB_DEF_PDU_EVENT_SHIFT 15
#define DB_DEF_PDU_CQPROC_SHIFT 16 #define DB_DEF_PDU_CQPROC_SHIFT 16
......
...@@ -809,14 +809,23 @@ static void hwi_ring_eq_db(struct beiscsi_hba *phba, ...@@ -809,14 +809,23 @@ static void hwi_ring_eq_db(struct beiscsi_hba *phba,
unsigned char rearm, unsigned char event) unsigned char rearm, unsigned char event)
{ {
u32 val = 0; u32 val = 0;
val |= id & DB_EQ_RING_ID_MASK;
if (rearm) if (rearm)
val |= 1 << DB_EQ_REARM_SHIFT; val |= 1 << DB_EQ_REARM_SHIFT;
if (clr_interrupt) if (clr_interrupt)
val |= 1 << DB_EQ_CLR_SHIFT; val |= 1 << DB_EQ_CLR_SHIFT;
if (event) if (event)
val |= 1 << DB_EQ_EVNT_SHIFT; val |= 1 << DB_EQ_EVNT_SHIFT;
val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
/* Setting lower order EQ_ID Bits */
val |= (id & DB_EQ_RING_ID_LOW_MASK);
/* Setting Higher order EQ_ID Bits */
val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
DB_EQ_RING_ID_HIGH_MASK)
<< DB_EQ_HIGH_SET_SHIFT);
iowrite32(val, phba->db_va + DB_EQ_OFFSET); iowrite32(val, phba->db_va + DB_EQ_OFFSET);
} }
...@@ -1098,15 +1107,25 @@ static int beiscsi_init_irqs(struct beiscsi_hba *phba) ...@@ -1098,15 +1107,25 @@ static int beiscsi_init_irqs(struct beiscsi_hba *phba)
return ret; return ret;
} }
static void hwi_ring_cq_db(struct beiscsi_hba *phba, void hwi_ring_cq_db(struct beiscsi_hba *phba,
unsigned int id, unsigned int num_processed, unsigned int id, unsigned int num_processed,
unsigned char rearm, unsigned char event) unsigned char rearm, unsigned char event)
{ {
u32 val = 0; u32 val = 0;
val |= id & DB_CQ_RING_ID_MASK;
if (rearm) if (rearm)
val |= 1 << DB_CQ_REARM_SHIFT; val |= 1 << DB_CQ_REARM_SHIFT;
val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
/* Setting lower order CQ_ID Bits */
val |= (id & DB_CQ_RING_ID_LOW_MASK);
/* Setting Higher order CQ_ID Bits */
val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
DB_CQ_RING_ID_HIGH_MASK)
<< DB_CQ_HIGH_SET_SHIFT);
iowrite32(val, phba->db_va + DB_CQ_OFFSET); iowrite32(val, phba->db_va + DB_CQ_OFFSET);
} }
......
...@@ -135,11 +135,15 @@ ...@@ -135,11 +135,15 @@
#define DB_RXULP0_OFFSET 0xA0 #define DB_RXULP0_OFFSET 0xA0
/********* Event Q door bell *************/ /********* Event Q door bell *************/
#define DB_EQ_OFFSET DB_CQ_OFFSET #define DB_EQ_OFFSET DB_CQ_OFFSET
#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ #define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
/* Clear the interrupt for this eq */ /* Clear the interrupt for this eq */
#define DB_EQ_CLR_SHIFT (9) /* bit 9 */ #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
/* Must be 1 */ /* Must be 1 */
#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
/* Higher Order EQ_ID bit */
#define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
#define DB_EQ_HIGH_SET_SHIFT 11
#define DB_EQ_HIGH_FEILD_SHIFT 9
/* Number of event entries processed */ /* Number of event entries processed */
#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
/* Rearm bit */ /* Rearm bit */
...@@ -147,7 +151,12 @@ ...@@ -147,7 +151,12 @@
/********* Compl Q door bell *************/ /********* Compl Q door bell *************/
#define DB_CQ_OFFSET 0x120 #define DB_CQ_OFFSET 0x120
#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ #define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
/* Higher Order CQ_ID bit */
#define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
#define DB_CQ_HIGH_SET_SHIFT 11
#define DB_CQ_HIGH_FEILD_SHIFT 10
/* Number of event entries processed */ /* Number of event entries processed */
#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
/* Rearm bit */ /* Rearm bit */
...@@ -821,6 +830,9 @@ void beiscsi_process_all_cqs(struct work_struct *work); ...@@ -821,6 +830,9 @@ void beiscsi_process_all_cqs(struct work_struct *work);
void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
struct iscsi_task *task); struct iscsi_task *task);
void hwi_ring_cq_db(struct beiscsi_hba *phba,
unsigned int id, unsigned int num_processed,
unsigned char rearm, unsigned char event);
static inline bool beiscsi_error(struct beiscsi_hba *phba) static inline bool beiscsi_error(struct beiscsi_hba *phba)
{ {
return phba->ue_detected || phba->fw_timeout; return phba->ue_detected || phba->fw_timeout;
......
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