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Commit e0a23ce2 authored by Paul Mundt's avatar Paul Mundt
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Merge branches 'common/pfc' and 'common/clkfwk' into rmobile/marzen 

Conflicts:
	arch/arm/mach-shmobile/clock-sh73a0.c
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parents 04cf3996 e499ada8 2dacb97d
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Showing with 442 additions and 218 deletions
arch/arm/mach-shmobile/clock-sh7372.c
View file @ e0a23ce2
......@@ -411,11 +411,11 @@ static struct clk *fsibckcr_parent[] = {
};
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
[DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
[DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
[DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
};
......
arch/arm/mach-shmobile/clock-sh73a0.c
View file @ e0a23ce2
......@@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
static unsigned long div7_recalc(struct clk *clk)
{
return clk->parent->rate / 7;
}
static struct clk_ops div7_clk_ops = {
.recalc = div7_recalc,
};
static unsigned long div13_recalc(struct clk *clk)
{
return clk->parent->rate / 13;
}
static struct clk_ops div13_clk_ops = {
.recalc = div13_recalc,
};
/* Divide extal1 by two */
static struct clk extal1_div2_clk = {
.ops = &div2_clk_ops,
......@@ -174,12 +192,29 @@ static struct clk pll3_clk = {
.enable_bit = 3,
};
/* Divide PLL1 by two */
/* Divide PLL */
static struct clk pll1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pll1_clk,
};
static struct clk pll1_div7_clk = {
.ops = &div7_clk_ops,
.parent = &pll1_clk,
};
static struct clk pll1_div13_clk = {
.ops = &div13_clk_ops,
.parent = &pll1_clk,
};
/* External input clock */
struct clk sh73a0_extcki_clk = {
};
struct clk sh73a0_extalr_clk = {
};
static struct clk *main_clks[] = {
&r_clk,
&sh73a0_extal1_clk,
......@@ -193,6 +228,10 @@ static struct clk *main_clks[] = {
&pll2_clk,
&pll3_clk,
&pll1_div2_clk,
&pll1_div7_clk,
&pll1_div13_clk,
&sh73a0_extcki_clk,
&sh73a0_extalr_clk,
};
static void div4_kick(struct clk *clk)
......@@ -246,27 +285,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
DIV6_NR };
static struct clk *vck_parent[8] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &sh73a0_extcki_clk,
[3] = &sh73a0_extal2_clk,
[4] = &main_div2_clk,
[5] = &sh73a0_extalr_clk,
[6] = &main_clk,
};
static struct clk *pll_parent[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &pll1_div13_clk,
};
static struct clk *hsi_parent[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &pll1_div7_clk,
};
static struct clk *pll_extal2_parent[] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &sh73a0_extal2_clk,
[3] = &sh73a0_extal2_clk,
};
static struct clk *dsi_parent[8] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &main_clk,
[3] = &sh73a0_extal2_clk,
[4] = &sh73a0_extcki_clk,
};
static struct clk div6_clks[DIV6_NR] = {
[DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
[DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT),
[DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
[DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
[DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
[DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
[DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
[DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
[DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
[DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
[DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
[DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
[DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
[DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
[DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
[DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
[DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
[DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
[DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
[DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
[DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
[DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
[DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
[DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
[DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
[DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
[DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
[DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
[DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
[DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
};
enum { MSTP001,
......@@ -403,7 +499,7 @@ void __init sh73a0_clock_init(void)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
......
arch/arm/mach-shmobile/include/mach/common.h
View file @ e0a23ce2
......@@ -46,6 +46,8 @@ extern void sh73a0_clock_init(void);
extern void sh73a0_pinmux_init(void);
extern struct clk sh73a0_extal1_clk;
extern struct clk sh73a0_extal2_clk;
extern struct clk sh73a0_extcki_clk;
extern struct clk sh73a0_extalr_clk;
extern unsigned int sh73a0_get_core_count(void);
extern void sh73a0_secondary_init(unsigned int cpu);
......
arch/sh/include/cpu-sh4/cpu/sh7724.h
View file @ e0a23ce2
......@@ -314,5 +314,6 @@ enum {
extern struct clk sh7724_fsimcka_clk;
extern struct clk sh7724_fsimckb_clk;
extern struct clk sh7724_dv_clki;
#endif /* __ASM_SH7724_H__ */
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
View file @ e0a23ce2
......@@ -233,73 +233,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
{
/* TMU0 */
.dev_id = "sh_tmu.0",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU1 */
.dev_id = "sh_tmu.1",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
}, {
/* TMU2 */
.dev_id = "sh_tmu.2",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU0],
},
CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
{
/* TMU3 */
.dev_id = "sh_tmu.3",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
}, {
/* TMU4 */
.dev_id = "sh_tmu.4",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
}, {
/* TMU5 */
.dev_id = "sh_tmu.5",
.con_id = "tmu_fck",
.clk = &mstp_clks[HWBLK_TMU1],
},
CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
{
/* SCIF0 */
.dev_id = "sh-sci.0",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF0],
}, {
/* SCIF1 */
.dev_id = "sh-sci.1",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF1],
}, {
/* SCIF2 */
.dev_id = "sh-sci.2",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF2],
}, {
/* SCIF3 */
.dev_id = "sh-sci.3",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF3],
}, {
/* SCIF4 */
.dev_id = "sh-sci.4",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF4],
}, {
/* SCIF5 */
.dev_id = "sh-sci.5",
.con_id = "sci_fck",
.clk = &mstp_clks[HWBLK_SCIF5],
},
CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
......@@ -324,6 +261,19 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
};
int __init arch_clk_init(void)
......
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
View file @ e0a23ce2
......@@ -111,13 +111,16 @@ static struct clk div3_clk = {
.parent = &pll_clk,
};
/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
/* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */
struct clk sh7724_fsimcka_clk = {
};
struct clk sh7724_fsimckb_clk = {
};
struct clk sh7724_dv_clki = {
};
static struct clk *main_clks[] = {
&r_clk,
&extal_clk,
......@@ -126,6 +129,7 @@ static struct clk *main_clks[] = {
&div3_clk,
&sh7724_fsimcka_clk,
&sh7724_fsimckb_clk,
&sh7724_dv_clki,
};
static void div4_kick(struct clk *clk)
......@@ -163,17 +167,20 @@ struct clk div4_clks[DIV4_NR] = {
[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
};
enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR };
static struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
/* Indices are important - they are the actual src selecting values */
static struct clk *common_parent[] = {
[0] = &div3_clk,
[1] = NULL,
};
enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
static struct clk *vclkcr_parent[8] = {
[0] = &div3_clk,
[2] = &sh7724_dv_clki,
[4] = &extal_clk,
};
/* Indices are important - they are the actual src selecting values */
static struct clk *fclkacr_parent[] = {
[0] = &div3_clk,
[1] = NULL,
......@@ -188,10 +195,16 @@ static struct clk *fclkbcr_parent[] = {
[3] = NULL,
};
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
[DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
static struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0,
vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3),
[DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0,
common_parent, ARRAY_SIZE(common_parent), 6, 1),
[DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
common_parent, ARRAY_SIZE(common_parent), 6, 1),
[DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0,
fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
[DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
[DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0,
fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
};
......@@ -269,8 +282,8 @@ static struct clk_lookup lookups[] = {
/* DIV6 clocks */
CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
......@@ -356,10 +369,7 @@ int __init arch_clk_init(void)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
......
drivers/sh/clk/core.c
View file @ e0a23ce2
......@@ -355,7 +355,7 @@ static int clk_establish_mapping(struct clk *clk)
*/
if (!clk->parent) {
clk->mapping = &dummy_mapping;
return 0;
goto out;
}
/*
......@@ -384,6 +384,9 @@ static int clk_establish_mapping(struct clk *clk)
}
clk->mapping = mapping;
out:
clk->mapped_reg = clk->mapping->base;
clk->mapped_reg += (phys_addr_t)clk->enable_reg - clk->mapping->phys;
return 0;
}
......@@ -402,10 +405,12 @@ static void clk_teardown_mapping(struct clk *clk)
/* Nothing to do */
if (mapping == &dummy_mapping)
return;
goto out;
kref_put(&mapping->ref, clk_destroy_mapping);
clk->mapping = NULL;
out:
clk->mapped_reg = NULL;
}
int clk_register(struct clk *clk)
......
drivers/sh/clk/cpg.c
View file @ e0a23ce2
......@@ -15,15 +15,15 @@
static int sh_clk_mstp32_enable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
clk->enable_reg);
iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
clk->mapped_reg);
return 0;
}
static void sh_clk_mstp32_disable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
clk->enable_reg);
iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
clk->mapped_reg);
}
static struct clk_ops sh_clk_mstp32_clk_ops = {
......@@ -72,7 +72,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk)
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
table, NULL);
idx = __raw_readl(clk->enable_reg) & 0x003f;
idx = ioread32(clk->mapped_reg) & 0x003f;
return clk->freq_table[idx].frequency;
}
......@@ -98,10 +98,10 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
if (ret < 0)
return ret;
value = __raw_readl(clk->enable_reg) &
value = ioread32(clk->mapped_reg) &
~(((1 << clk->src_width) - 1) << clk->src_shift);
__raw_writel(value | (i << clk->src_shift), clk->enable_reg);
iowrite32(value | (i << clk->src_shift), clk->mapped_reg);
/* Rebuild the frequency table */
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
......@@ -119,10 +119,10 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
if (idx < 0)
return idx;
value = __raw_readl(clk->enable_reg);
value = ioread32(clk->mapped_reg);
value &= ~0x3f;
value |= idx;
__raw_writel(value, clk->enable_reg);
iowrite32(value, clk->mapped_reg);
return 0;
}
......@@ -133,9 +133,9 @@ static int sh_clk_div6_enable(struct clk *clk)
ret = sh_clk_div6_set_rate(clk, clk->rate);
if (ret == 0) {
value = __raw_readl(clk->enable_reg);
value = ioread32(clk->mapped_reg);
value &= ~0x100; /* clear stop bit to enable clock */
__raw_writel(value, clk->enable_reg);
iowrite32(value, clk->mapped_reg);
}
return ret;
}
......@@ -144,10 +144,10 @@ static void sh_clk_div6_disable(struct clk *clk)
{
unsigned long value;
value = __raw_readl(clk->enable_reg);
value = ioread32(clk->mapped_reg);
value |= 0x100; /* stop clock */
value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
__raw_writel(value, clk->enable_reg);
iowrite32(value, clk->mapped_reg);
}
static struct clk_ops sh_clk_div6_clk_ops = {
......@@ -167,6 +167,38 @@ static struct clk_ops sh_clk_div6_reparent_clk_ops = {
.set_parent = sh_clk_div6_set_parent,
};
static int __init sh_clk_init_parent(struct clk *clk)
{
u32 val;
if (clk->parent)
return 0;
if (!clk->parent_table || !clk->parent_num)
return 0;
if (!clk->src_width) {
pr_err("sh_clk_init_parent: cannot select parent clock\n");
return -EINVAL;
}
val = (ioread32(clk->mapped_reg) >> clk->src_shift);
val &= (1 << clk->src_width) - 1;
if (val >= clk->parent_num) {
pr_err("sh_clk_init_parent: parent table size failed\n");
return -EINVAL;
}
clk->parent = clk->parent_table[val];
if (!clk->parent) {
pr_err("sh_clk_init_parent: unable to set parent");
return -EINVAL;
}
return 0;
}
static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
struct clk_ops *ops)
{
......@@ -190,6 +222,9 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
clkp->ops = ops;
clkp->freq_table = freq_table + (k * freq_table_size);
clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
ret = sh_clk_init_parent(clkp);
if (ret < 0)
break;
ret = clk_register(clkp);
}
......@@ -217,7 +252,7 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
table, &clk->arch_flags);
idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
idx = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0x000f;
return clk->freq_table[idx].frequency;
}
......@@ -235,15 +270,15 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
*/
if (parent->flags & CLK_ENABLE_ON_INIT)
value = __raw_readl(clk->enable_reg) & ~(1 << 7);
value = ioread32(clk->mapped_reg) & ~(1 << 7);
else
value = __raw_readl(clk->enable_reg) | (1 << 7);
value = ioread32(clk->mapped_reg) | (1 << 7);
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
__raw_writel(value, clk->enable_reg);
iowrite32(value, clk->mapped_reg);
/* Rebiuld the frequency table */
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
......@@ -260,10 +295,10 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
if (idx < 0)
return idx;
value = __raw_readl(clk->enable_reg);
value = ioread32(clk->mapped_reg);
value &= ~(0xf << clk->enable_bit);
value |= (idx << clk->enable_bit);
__raw_writel(value, clk->enable_reg);
iowrite32(value, clk->mapped_reg);
if (d4t->kick)
d4t->kick(clk);
......@@ -273,13 +308,13 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
static int sh_clk_div4_enable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
iowrite32(ioread32(clk->mapped_reg) & ~(1 << 8), clk->mapped_reg);
return 0;
}
static void sh_clk_div4_disable(struct clk *clk)
{
__raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg);
}
static struct clk_ops sh_clk_div4_clk_ops = {
......
drivers/sh/pfc.c
View file @ e0a23ce2
This diff is collapsed.
include/linux/sh_clk.h
View file @ e0a23ce2
......@@ -49,6 +49,7 @@ struct clk {
void __iomem *enable_reg;
unsigned int enable_bit;
void __iomem *mapped_reg;
unsigned long arch_flags;
void *priv;
......@@ -131,10 +132,9 @@ int sh_clk_div4_enable_register(struct clk *clks, int nr,
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
struct clk_div4_table *table);
#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \
#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
_num_parents, _src_shift, _src_width) \
{ \
.parent = _parent, \
.enable_reg = (void __iomem *)_reg, \
.flags = _flags, \
.parent_table = _parents, \
......@@ -144,7 +144,11 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
}
#define SH_CLK_DIV6(_parent, _reg, _flags) \
SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
{ \
.parent = _parent, \
.enable_reg = (void __iomem *)_reg, \
.flags = _flags, \
}
int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);
......
include/linux/sh_pfc.h
View file @ e0a23ce2
......@@ -45,16 +45,24 @@ struct pinmux_cfg_reg {
unsigned long reg, reg_width, field_width;
unsigned long *cnt;
pinmux_enum_t *enum_ids;
unsigned long *var_field_width;
};
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
.cnt = (unsigned long [r_width / f_width]) {}, \
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.cnt = (unsigned long [r_width]) {}, \
.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
.enum_ids = (pinmux_enum_t [])
struct pinmux_data_reg {
unsigned long reg, reg_width, reg_shadow;
pinmux_enum_t *enum_ids;
void __iomem *mapped_reg;
};
#define PINMUX_DATA_REG(name, r, r_width) \
......@@ -75,6 +83,12 @@ struct pinmux_range {
pinmux_enum_t force;
};
struct pfc_window {
phys_addr_t phys;
void __iomem *virt;
unsigned long size;
};
struct pinmux_info {
char *name;
pinmux_enum_t reserved_id;
......@@ -98,6 +112,12 @@ struct pinmux_info {
struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
struct resource *resource;
unsigned int num_resources;
struct pfc_window *window;
unsigned long unlock_reg;
struct gpio_chip chip;
};
......
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