ARM: tegra: apalis-tk1: reorder cpu dfll clock properties

Reorder CPU DFLL clock properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi

@@ -1925,8 +1925,8 @@ sdhci@700b0600 {
 	/* CPU DFLL clock */
 	clock@70110000 {
 		status = "okay";
-		vdd-cpu-supply = <&reg_vdd_cpu>;
 		nvidia,i2c-fs-rate = <400000>;
+		vdd-cpu-supply = <&reg_vdd_cpu>;
 	};
 
 	ahub@70300000 {

arch/arm/boot/dts/tegra124-apalis.dtsi

@@ -1954,8 +1954,8 @@ sdhci@700b0600 {
 	/* CPU DFLL clock */
 	clock@70110000 {
 		status = "okay";
-		vdd-cpu-supply = <&reg_vdd_cpu>;
 		nvidia,i2c-fs-rate = <400000>;
+		vdd-cpu-supply = <&reg_vdd_cpu>;
 	};
 
 	ahub@70300000 {