Commit e1be65a5 authored by Baruch Siach's avatar Baruch Siach Committed by Eric Anholt

ARM: dts: bcm2835: fix uart0/uart1 pins

According to the BCM2835 ARM Peripherals document uart1 doesn't map to pins
36-39, but uart0 does.

Also, split into separate Rx/Tx and CST/RTS groups to match other uart nodes.

Fixes: 21ff8439 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.")
Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
parent 843b2287
...@@ -309,6 +309,14 @@ uart0_gpio32: uart0_gpio32 { ...@@ -309,6 +309,14 @@ uart0_gpio32: uart0_gpio32 {
brcm,pins = <32 33>; brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>; brcm,function = <BCM2835_FSEL_ALT3>;
}; };
uart0_gpio36: uart0_gpio36 {
brcm,pins = <36 37>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
brcm,pins = <38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio14: uart1_gpio14 { uart1_gpio14: uart1_gpio14 {
brcm,pins = <14 15>; brcm,pins = <14 15>;
...@@ -326,10 +334,6 @@ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { ...@@ -326,10 +334,6 @@ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
brcm,pins = <30 31>; brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT5>; brcm,function = <BCM2835_FSEL_ALT5>;
}; };
uart1_gpio36: uart1_gpio36 {
brcm,pins = <36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio40: uart1_gpio40 { uart1_gpio40: uart1_gpio40 {
brcm,pins = <40 41>; brcm,pins = <40 41>;
brcm,function = <BCM2835_FSEL_ALT5>; brcm,function = <BCM2835_FSEL_ALT5>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment