Commit e32b16c3 authored by Prashant Malani's avatar Prashant Malani Committed by Enric Balletbo i Serra

platform/chrome: cros_ec: Update mux state bits

Sync the EC_CMD_USB_PD_MUX_INFO mux state bit fields with the Chrome EC
code base. The newly added bit fields will be used for cros-ec-typec mux
control.
Signed-off-by: default avatarPrashant Malani <pmalani@chromium.org>
Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
parent f28adb41
...@@ -5207,11 +5207,15 @@ struct ec_params_usb_pd_mux_info { ...@@ -5207,11 +5207,15 @@ struct ec_params_usb_pd_mux_info {
} __ec_align1; } __ec_align1;
/* Flags representing mux state */ /* Flags representing mux state */
#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ #define USB_PD_MUX_NONE 0 /* Open switch */
#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ #define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ #define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ #define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ #define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
struct ec_response_usb_pd_mux_info { struct ec_response_usb_pd_mux_info {
uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */
......
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