Commit e3851447 authored by Ben Cahill's avatar Ben Cahill Committed by David S. Miller

iwlwifi: document 4965 Tx scheduler

Document 4965 Tx scheduler
Signed-off-by: default avatarBen Cahill <ben.m.cahill@intel.com>
Signed-off-by: default avatarZhu Yi <yi.zhu@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 5d5456fe
This diff is collapsed.
...@@ -63,7 +63,10 @@ ...@@ -63,7 +63,10 @@
#ifndef __iwl_prph_h__ #ifndef __iwl_prph_h__
#define __iwl_prph_h__ #define __iwl_prph_h__
/*
* Registers in this file are internal, not PCI bus memory mapped.
* Driver accesses these via HBUS_TARG_PRPH_* registers.
*/
#define PRPH_BASE (0x00000) #define PRPH_BASE (0x00000)
#define PRPH_END (0xFFFFF) #define PRPH_END (0xFFFFF)
...@@ -225,8 +228,8 @@ ...@@ -225,8 +228,8 @@
#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
#define BSM_SRAM_SIZE (1024) /* bytes */ #define BSM_SRAM_SIZE (1024) /* bytes */
/* ALM SCD */
/* SCD (Scheduler) */ /* 3945 Tx scheduler registers */
#define ALM_SCD_BASE (PRPH_BASE + 0x2E00) #define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000) #define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004) #define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
...@@ -236,7 +239,10 @@ ...@@ -236,7 +239,10 @@
#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) #define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) #define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
/* 4965 SCD memory mapped registers */ /*
* 4965 Tx Scheduler registers.
* Details are documented in iwl-4965-hw.h
*/
#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00) #define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
#define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0) #define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0)
......
...@@ -201,6 +201,8 @@ static void iwl4965_print_hex_dump(int level, void *p, u32 len) ...@@ -201,6 +201,8 @@ static void iwl4965_print_hex_dump(int level, void *p, u32 len)
* The 4965 operates with up to 17 queues: One receive queue, one transmit * The 4965 operates with up to 17 queues: One receive queue, one transmit
* queue (#4) for sending commands to the device firmware, and 15 other * queue (#4) for sending commands to the device firmware, and 15 other
* Tx queues that may be mapped to prioritized Tx DMA/FIFO channels. * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
*
* See more detailed info in iwl-4965-hw.h.
***************************************************/ ***************************************************/
static int iwl4965_queue_space(const struct iwl4965_queue *q) static int iwl4965_queue_space(const struct iwl4965_queue *q)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment