Commit e6aacf9a authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman

dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks

According to the latest information, the clock options for CAN on RZ/G2
are the same as the ones available on R-Car Gen3

Fixes: 868b7c0f ("dt-bindings: can: rcar_can: Add r8a774a1 support")
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarChris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 9d79b2f1
...@@ -27,13 +27,8 @@ Required properties: ...@@ -27,13 +27,8 @@ Required properties:
- reg: physical base address and size of the R-Car CAN register map. - reg: physical base address and size of the R-Car CAN register map.
- interrupts: interrupt specifier for the sole interrupt. - interrupts: interrupt specifier for the sole interrupt.
- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2 - clocks: phandles and clock specifiers for 3 CAN clock inputs.
devices. - clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
phandles and clock specifiers for 3 CAN clock inputs for every other
SoC.
- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk".
3 clock input name strings for every other SoC: "clkp1", "clkp2",
"can_clk".
- pinctrl-0: pin control group to be used for this controller. - pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must be "default". - pinctrl-names: must be "default".
...@@ -49,8 +44,7 @@ using the below properties: ...@@ -49,8 +44,7 @@ using the below properties:
Optional properties: Optional properties:
- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
<0x0> (default) : Peripheral clock (clkp1) <0x0> (default) : Peripheral clock (clkp1)
<0x1> : Peripheral clock (clkp2) (not supported by <0x1> : Peripheral clock (clkp2)
RZ/G2 devices)
<0x3> : External input clock <0x3> : External input clock
Example Example
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment