Commit e8510d43 authored by Tim Harvey's avatar Tim Harvey Committed by Mark Brown

spi: spi-cavium-thunderx: flag controller as half duplex

The OcteonTX (TX1/ThunderX) SPI controller does not support full
duplex transactions. Set the appropriate flag such that the spi
core will return -EINVAL on such transactions requested by chip
drivers.

This is an RFC as I need someone from Marvell/Cavium to confirm
if this driver is used for other silicon that does support
full duplex transfers (in which case we will need to identify
that we are running on the ThunderX arch before setting the flag).
Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Cc: Robert Richter <rrichter@marvell.com>
Link: https://lore.kernel.org/r/1590680799-5640-1-git-send-email-tharvey@gateworks.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent eb8d6d46
...@@ -64,6 +64,7 @@ static int thunderx_spi_probe(struct pci_dev *pdev, ...@@ -64,6 +64,7 @@ static int thunderx_spi_probe(struct pci_dev *pdev,
p->sys_freq = SYS_FREQ_DEFAULT; p->sys_freq = SYS_FREQ_DEFAULT;
dev_info(dev, "Set system clock to %u\n", p->sys_freq); dev_info(dev, "Set system clock to %u\n", p->sys_freq);
master->flags = SPI_MASTER_HALF_DUPLEX;
master->num_chipselect = 4; master->num_chipselect = 4;
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
SPI_LSB_FIRST | SPI_3WIRE; SPI_LSB_FIRST | SPI_3WIRE;
......
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