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Commit e8515021 authored by Ben Collins's avatar Ben Collins Committed by Keith M. Wesolowski
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[VIDEO]: Revert atyfb back to known working clean base.

parent cac13976
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Showing with 257 additions and 436 deletions
drivers/video/aty/Makefile
View file @ e8515021
...@@ -4,5 +4,4 @@ obj-$(CONFIG_FB_ATY128) += aty128fb.o ...@@ -4,5 +4,4 @@ obj-$(CONFIG_FB_ATY128) += aty128fb.o
atyfb-y := atyfb_base.o mach64_accel.o atyfb-y := atyfb_base.o mach64_accel.o
atyfb-$(CONFIG_FB_ATY_GX) += mach64_gx.o atyfb-$(CONFIG_FB_ATY_GX) += mach64_gx.o
atyfb-$(CONFIG_FB_ATY_CT) += mach64_ct.o mach64_cursor.o atyfb-$(CONFIG_FB_ATY_CT) += mach64_ct.o mach64_cursor.o
atyfb-$(CONFIG_FB_ATY_XL_INIT) += xlinit.o
atyfb-objs := $(atyfb-y) atyfb-objs := $(atyfb-y)
drivers/video/aty/atyfb.h
View file @ e8515021
...@@ -36,17 +36,13 @@ struct pll_ct { ...@@ -36,17 +36,13 @@ struct pll_ct {
u8 pll_ref_div; u8 pll_ref_div;
u8 pll_gen_cntl; u8 pll_gen_cntl;
u8 mclk_fb_div; u8 mclk_fb_div;
u8 mclk_fb_mult; /* 2 ro 4 */
u8 sclk_fb_div;
u8 pll_vclk_cntl; u8 pll_vclk_cntl;
u8 vclk_post_div; u8 vclk_post_div;
u8 vclk_fb_div; u8 vclk_fb_div;
u8 pll_ext_cntl; u8 pll_ext_cntl;
u8 spll_cntl2;
u32 dsp_config; /* Mach64 GTB DSP */ u32 dsp_config; /* Mach64 GTB DSP */
u32 dsp_on_off; /* Mach64 GTB DSP */ u32 dsp_on_off; /* Mach64 GTB DSP */
u8 mclk_post_div_real; u8 mclk_post_div_real;
u8 xclk_post_div_real;
u8 vclk_post_div_real; u8 vclk_post_div_real;
}; };
...@@ -79,7 +75,6 @@ struct atyfb_par { ...@@ -79,7 +75,6 @@ struct atyfb_par {
u32 ref_clk_per; u32 ref_clk_per;
u32 pll_per; u32 pll_per;
u32 mclk_per; u32 mclk_per;
u32 xclk_per;
u8 bus_type; u8 bus_type;
u8 ram_type; u8 ram_type;
u8 mem_refresh_rate; u8 mem_refresh_rate;
...@@ -123,7 +118,7 @@ struct atyfb_par { ...@@ -123,7 +118,7 @@ struct atyfb_par {
#define M64F_EXTRA_BRIGHT 0x00020000 #define M64F_EXTRA_BRIGHT 0x00020000
#define M64F_LT_SLEEP 0x00040000 #define M64F_LT_SLEEP 0x00040000
#define M64F_XL_DLL 0x00080000 #define M64F_XL_DLL 0x00080000
#define M64F_MFB_TIMES_4 0x00100000
/* /*
* Register access * Register access
...@@ -156,33 +151,6 @@ static inline void aty_st_le32(int regindex, u32 val, ...@@ -156,33 +151,6 @@ static inline void aty_st_le32(int regindex, u32 val,
#endif #endif
} }
static inline u16 aty_ld_le16(int regindex, const struct atyfb_par *par)
{
/* Hack for bloc 1, should be cleanly optimized by compiler */
if (regindex >= 0x400)
regindex -= 0x800;
#if defined(__mc68000__)
return le16_to_cpu(*((volatile u16 *)(par->ati_regbase + regindex)));
#else
return readw(par->ati_regbase + regindex);
#endif
}
static inline void aty_st_le16(int regindex, u16 val,
const struct atyfb_par *par)
{
/* Hack for bloc 1, should be cleanly optimized by compiler */
if (regindex >= 0x400)
regindex -= 0x800;
#if defined(__mc68000__)
*((volatile u16 *)(par->ati_regbase + regindex)) = cpu_to_le16(val);
#else
writew(val, par->ati_regbase + regindex);
#endif
}
static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par) static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
{ {
/* Hack for bloc 1, should be cleanly optimized by compiler */ /* Hack for bloc 1, should be cleanly optimized by compiler */
...@@ -221,19 +189,6 @@ static inline u8 aty_ld_pll(int offset, const struct atyfb_par *par) ...@@ -221,19 +189,6 @@ static inline u8 aty_ld_pll(int offset, const struct atyfb_par *par)
} }
/*
* CT Family only.
*/
static inline void aty_st_pll(int offset, u8 val,
const struct atyfb_par *par)
{
/* write addr byte */
aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, par);
/* write the register value */
aty_st_8(CLOCK_CNTL + 2, val, par);
aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, par);
}
/* /*
* DAC operations * DAC operations
*/ */
......
drivers/video/aty/atyfb_base.c
View file @ e8515021
This diff is collapsed.
drivers/video/aty/mach64_ct.c
View file @ e8515021
This diff is collapsed.
drivers/video/aty/mach64_cursor.c
View file @ e8515021
...@@ -135,10 +135,6 @@ static void aty_set_cursor(struct fb_info *info) ...@@ -135,10 +135,6 @@ static void aty_set_cursor(struct fb_info *info)
yoff = 0; yoff = 0;
} }
/* In doublescan mode, the cursor location also needs to be
doubled. */
if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
y<<=1;
wait_for_fifo(4, par); wait_for_fifo(4, par);
aty_st_le32(CUR_OFFSET, (info->fix.smem_len >> 3) + (yoff << 1), aty_st_le32(CUR_OFFSET, (info->fix.smem_len >> 3) + (yoff << 1),
par); par);
...@@ -168,7 +164,7 @@ int atyfb_cursor(struct fb_info *info, struct fb_cursor *cursor) ...@@ -168,7 +164,7 @@ int atyfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
#ifdef __sparc__ #ifdef __sparc__
if (par->mmaped) if (par->mmaped)
return; return 0;
#endif #endif
aty_set_cursor(info); aty_set_cursor(info);
...@@ -192,7 +188,7 @@ struct aty_cursor *__init aty_init_cursor(struct fb_info *info) ...@@ -192,7 +188,7 @@ struct aty_cursor *__init aty_init_cursor(struct fb_info *info)
info->fix.smem_len -= PAGE_SIZE; info->fix.smem_len -= PAGE_SIZE;
#ifdef __sparc__ #ifdef __sparc__
addr = info->screen_base - 0x800000 + info->fix.smem_len; addr = (unsigned long) info->screen_base - 0x800000 + info->fix.smem_len;
cursor->ram = (u8 *) addr; cursor->ram = (u8 *) addr;
#else #else
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
......
drivers/video/aty/mach64_gx.c
View file @ e8515021
/* /*
* ATI Mach64 GX Support * ATI Mach64 GX Support
*/ */
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/fb.h> #include <linux/fb.h>
#include <linux/sched.h>
#include <asm/io.h> #include <asm/io.h>
...@@ -337,8 +339,8 @@ const struct aty_dac_ops aty_dac_att21c498 = { ...@@ -337,8 +339,8 @@ const struct aty_dac_ops aty_dac_att21c498 = {
* ATI 18818 / ICS 2595 Clock Chip * ATI 18818 / ICS 2595 Clock Chip
*/ */
static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per, static int aty_var_to_pll_18818(const struct fb_info *info,
u8 bpp, union aty_pll *pll) u32 vclk_per, u8 bpp, union aty_pll *pll)
{ {
u32 MHz100; /* in 0.01 MHz */ u32 MHz100; /* in 0.01 MHz */
u32 program_bits; u32 program_bits;
...@@ -493,7 +495,7 @@ const struct aty_pll_ops aty_pll_ati18818_1 = { ...@@ -493,7 +495,7 @@ const struct aty_pll_ops aty_pll_ati18818_1 = {
* STG 1703 Clock Chip * STG 1703 Clock Chip
*/ */
static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per, static int aty_var_to_pll_1703(const struct fb_info *info,
u32 vclk_per, u8 bpp, union aty_pll *pll) u32 vclk_per, u8 bpp, union aty_pll *pll)
{ {
u32 mhz100; /* in 0.01 MHz */ u32 mhz100; /* in 0.01 MHz */
...@@ -609,7 +611,7 @@ const struct aty_pll_ops aty_pll_stg1703 = { ...@@ -609,7 +611,7 @@ const struct aty_pll_ops aty_pll_stg1703 = {
* Chrontel 8398 Clock Chip * Chrontel 8398 Clock Chip
*/ */
static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per, static int aty_var_to_pll_8398(const struct fb_info *info,
u32 vclk_per, u8 bpp, union aty_pll *pll) u32 vclk_per, u8 bpp, union aty_pll *pll)
{ {
u32 tempA, tempB, fOut, longMHz100, diff, preDiff; u32 tempA, tempB, fOut, longMHz100, diff, preDiff;
......
include/video/mach64.h
View file @ e8515021
...@@ -558,7 +558,7 @@ ...@@ -558,7 +558,7 @@
#define CRTC_CSYNC_EN 0x00000010 #define CRTC_CSYNC_EN 0x00000010
#define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */ #define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */
#define CRTC_DISPLAY_DIS 0x00000040 #define CRTC_DISPLAY_DIS 0x00000040
#define CRTC_VGA_XOVERSCAN 0x00000080 #define CRTC_VGA_XOVERSCAN 0x00000040
#define CRTC_PIX_WIDTH_MASK 0x00000700 #define CRTC_PIX_WIDTH_MASK 0x00000700
#define CRTC_PIX_WIDTH_4BPP 0x00000100 #define CRTC_PIX_WIDTH_4BPP 0x00000100
...@@ -849,19 +849,7 @@ ...@@ -849,19 +849,7 @@
#define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */ #define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */
#define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */ #define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */
#define LT_CHIP_ID 0x4c54 /* RAGE LT */ #define LT_CHIP_ID 0x4c54 /* RAGE LT */
#define XL_CHIP_ID 0x4752 /* RAGE (XL) */
/* mach64CT family / (Rage XL) class */
#define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */
#define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */
#define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */
#define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */
#define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */
#define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */
#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
(id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
(id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
#define GT_CHIP_ID 0x4754 /* RAGE (GT) */ #define GT_CHIP_ID 0x4754 /* RAGE (GT) */
#define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */ #define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */
#define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */ #define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */
...@@ -1160,65 +1148,6 @@ ...@@ -1160,65 +1148,6 @@
#define APC_LUT_MN 0x39 #define APC_LUT_MN 0x39
#define APC_LUT_OP 0x3A #define APC_LUT_OP 0x3A
/* Values in LCD_GEN_CTRL */
#define CRT_ON 0x00000001ul
#define LCD_ON 0x00000002ul
#define HORZ_DIVBY2_EN 0x00000004ul
#define DONT_DS_ICON 0x00000008ul
#define LOCK_8DOT 0x00000010ul
#define ICON_ENABLE 0x00000020ul
#define DONT_SHADOW_VPAR 0x00000040ul
#define V2CLK_PM_EN 0x00000080ul
#define RST_FM 0x00000100ul
#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */
#define DIS_HOR_CRT_DIVBY2 0x00000400ul
#define SCLK_SEL 0x00000800ul
#define SCLK_DELAY 0x0000f000ul
#define TVCLK_PM_EN 0x00010000ul
#define VCLK_DAC_PM_EN 0x00020000ul
#define VCLK_LCD_OFF 0x00040000ul
#define SELECT_WAIT_4MS 0x00080000ul
#define XTALIN_PM_EN 0x00080000ul /* XC/XL */
#define V2CLK_DAC_PM_EN 0x00100000ul
#define LVDS_EN 0x00200000ul
#define LVDS_PLL_EN 0x00400000ul
#define LVDS_PLL_RESET 0x00800000ul
#define LVDS_RESERVED_BITS 0x07000000ul
#define CRTC_RW_SELECT 0x08000000ul /* LTPro */
#define USE_SHADOWED_VEND 0x10000000ul
#define USE_SHADOWED_ROWCUR 0x20000000ul
#define SHADOW_EN 0x40000000ul
#define SHADOW_RW_EN 0x80000000ul
/* Values in HORZ_STRETCHING */
#define HORZ_STRETCH_BLEND 0x00000ffful
#define HORZ_STRETCH_RATIO 0x0000fffful
#define HORZ_STRETCH_LOOP 0x00070000ul
#define HORZ_STRETCH_LOOP09 0x00000000ul
#define HORZ_STRETCH_LOOP11 0x00010000ul
#define HORZ_STRETCH_LOOP12 0x00020000ul
#define HORZ_STRETCH_LOOP14 0x00030000ul
#define HORZ_STRETCH_LOOP15 0x00040000ul
/* ? 0x00050000ul */
/* ? 0x00060000ul */
/* ? 0x00070000ul */
/* ? 0x00080000ul */
#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */
/* ? 0x10000000ul */
#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */
#define HORZ_STRETCH_MODE 0x40000000ul
#define HORZ_STRETCH_EN 0x80000000ul
/* Values in VERT_STRETCHING */
#define VERT_STRETCH_RATIO0 0x000003fful
#define VERT_STRETCH_RATIO1 0x000ffc00ul
#define VERT_STRETCH_RATIO2 0x3ff00000ul
#define VERT_STRETCH_USE0 0x40000000ul
#define VERT_STRETCH_EN 0x80000000ul
/* Values in EXT_VERT_STRETCH */
#define AUTO_VERT_RATIO 0x00400000ul
#define VERT_STRETCH_MODE 0x00000400ul
/* Values in LCD_MISC_CNTL */ /* Values in LCD_MISC_CNTL */
#define BIAS_MOD_LEVEL_MASK 0x0000ff00 #define BIAS_MOD_LEVEL_MASK 0x0000ff00
......
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