Commit e948990f authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'x86-fixes-for-linus' of...

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: fix early panic with boot option "nosmp"
  x86/oprofile: fix Intel cpu family 6 detection
  oprofile: fix CPU unplug panic in ppro_stop()
  AMD IOMMU: fix possible race while accessing iommu->need_sync
  AMD IOMMU: set device table entry for aliased devices
  AMD IOMMU: struct amd_iommu remove padding on 64 bit
  x86: fix broken flushing in GART nofullflush path
  x86: fix dma_mapping_error for 32bit x86
parents 2b218aea 9adc1386
...@@ -251,13 +251,6 @@ struct amd_iommu { ...@@ -251,13 +251,6 @@ struct amd_iommu {
/* Pointer to PCI device of this IOMMU */ /* Pointer to PCI device of this IOMMU */
struct pci_dev *dev; struct pci_dev *dev;
/*
* Capability pointer. There could be more than one IOMMU per PCI
* device function if there are more than one AMD IOMMU capability
* pointers.
*/
u16 cap_ptr;
/* physical address of MMIO space */ /* physical address of MMIO space */
u64 mmio_phys; u64 mmio_phys;
/* virtual address of MMIO space */ /* virtual address of MMIO space */
...@@ -266,6 +259,13 @@ struct amd_iommu { ...@@ -266,6 +259,13 @@ struct amd_iommu {
/* capabilities of that IOMMU read from ACPI */ /* capabilities of that IOMMU read from ACPI */
u32 cap; u32 cap;
/*
* Capability pointer. There could be more than one IOMMU per PCI
* device function if there are more than one AMD IOMMU capability
* pointers.
*/
u16 cap_ptr;
/* pci domain of this IOMMU */ /* pci domain of this IOMMU */
u16 pci_seg; u16 pci_seg;
...@@ -284,19 +284,19 @@ struct amd_iommu { ...@@ -284,19 +284,19 @@ struct amd_iommu {
/* size of command buffer */ /* size of command buffer */
u32 cmd_buf_size; u32 cmd_buf_size;
/* event buffer virtual address */
u8 *evt_buf;
/* size of event buffer */ /* size of event buffer */
u32 evt_buf_size; u32 evt_buf_size;
/* event buffer virtual address */
u8 *evt_buf;
/* MSI number for event interrupt */ /* MSI number for event interrupt */
u16 evt_msi_num; u16 evt_msi_num;
/* if one, we need to send a completion wait command */
int need_sync;
/* true if interrupts for this IOMMU are already enabled */ /* true if interrupts for this IOMMU are already enabled */
bool int_enabled; bool int_enabled;
/* if one, we need to send a completion wait command */
int need_sync;
/* default dma_ops domain for that IOMMU */ /* default dma_ops domain for that IOMMU */
struct dma_ops_domain *default_dom; struct dma_ops_domain *default_dom;
}; };
......
...@@ -71,15 +71,13 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev) ...@@ -71,15 +71,13 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
/* Make sure we keep the same behaviour */ /* Make sure we keep the same behaviour */
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{ {
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_64
return 0;
#else
struct dma_mapping_ops *ops = get_dma_ops(dev); struct dma_mapping_ops *ops = get_dma_ops(dev);
if (ops->mapping_error) if (ops->mapping_error)
return ops->mapping_error(dev, dma_addr); return ops->mapping_error(dev, dma_addr);
return (dma_addr == bad_dma_address);
#endif #endif
return (dma_addr == bad_dma_address);
} }
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
......
...@@ -187,6 +187,8 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) ...@@ -187,6 +187,8 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
spin_lock_irqsave(&iommu->lock, flags); spin_lock_irqsave(&iommu->lock, flags);
ret = __iommu_queue_command(iommu, cmd); ret = __iommu_queue_command(iommu, cmd);
if (!ret)
iommu->need_sync = 1;
spin_unlock_irqrestore(&iommu->lock, flags); spin_unlock_irqrestore(&iommu->lock, flags);
return ret; return ret;
...@@ -210,10 +212,13 @@ static int iommu_completion_wait(struct amd_iommu *iommu) ...@@ -210,10 +212,13 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
iommu->need_sync = 0;
spin_lock_irqsave(&iommu->lock, flags); spin_lock_irqsave(&iommu->lock, flags);
if (!iommu->need_sync)
goto out;
iommu->need_sync = 0;
ret = __iommu_queue_command(iommu, &cmd); ret = __iommu_queue_command(iommu, &cmd);
if (ret) if (ret)
...@@ -254,8 +259,6 @@ static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) ...@@ -254,8 +259,6 @@ static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
ret = iommu_queue_command(iommu, &cmd); ret = iommu_queue_command(iommu, &cmd);
iommu->need_sync = 1;
return ret; return ret;
} }
...@@ -281,8 +284,6 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, ...@@ -281,8 +284,6 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
ret = iommu_queue_command(iommu, &cmd); ret = iommu_queue_command(iommu, &cmd);
iommu->need_sync = 1;
return ret; return ret;
} }
...@@ -762,8 +763,6 @@ static void set_device_domain(struct amd_iommu *iommu, ...@@ -762,8 +763,6 @@ static void set_device_domain(struct amd_iommu *iommu,
write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
iommu_queue_inv_dev_entry(iommu, devid); iommu_queue_inv_dev_entry(iommu, devid);
iommu->need_sync = 1;
} }
/***************************************************************************** /*****************************************************************************
...@@ -858,6 +857,9 @@ static int get_device_resources(struct device *dev, ...@@ -858,6 +857,9 @@ static int get_device_resources(struct device *dev,
print_devid(_bdf, 1); print_devid(_bdf, 1);
} }
if (domain_for_device(_bdf) == NULL)
set_device_domain(*iommu, *domain, _bdf);
return 1; return 1;
} }
...@@ -1031,8 +1033,7 @@ static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, ...@@ -1031,8 +1033,7 @@ static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
if (addr == bad_dma_address) if (addr == bad_dma_address)
goto out; goto out;
if (unlikely(iommu->need_sync)) iommu_completion_wait(iommu);
iommu_completion_wait(iommu);
out: out:
spin_unlock_irqrestore(&domain->lock, flags); spin_unlock_irqrestore(&domain->lock, flags);
...@@ -1060,8 +1061,7 @@ static void unmap_single(struct device *dev, dma_addr_t dma_addr, ...@@ -1060,8 +1061,7 @@ static void unmap_single(struct device *dev, dma_addr_t dma_addr,
__unmap_single(iommu, domain->priv, dma_addr, size, dir); __unmap_single(iommu, domain->priv, dma_addr, size, dir);
if (unlikely(iommu->need_sync)) iommu_completion_wait(iommu);
iommu_completion_wait(iommu);
spin_unlock_irqrestore(&domain->lock, flags); spin_unlock_irqrestore(&domain->lock, flags);
} }
...@@ -1127,8 +1127,7 @@ static int map_sg(struct device *dev, struct scatterlist *sglist, ...@@ -1127,8 +1127,7 @@ static int map_sg(struct device *dev, struct scatterlist *sglist,
goto unmap; goto unmap;
} }
if (unlikely(iommu->need_sync)) iommu_completion_wait(iommu);
iommu_completion_wait(iommu);
out: out:
spin_unlock_irqrestore(&domain->lock, flags); spin_unlock_irqrestore(&domain->lock, flags);
...@@ -1173,8 +1172,7 @@ static void unmap_sg(struct device *dev, struct scatterlist *sglist, ...@@ -1173,8 +1172,7 @@ static void unmap_sg(struct device *dev, struct scatterlist *sglist,
s->dma_address = s->dma_length = 0; s->dma_address = s->dma_length = 0;
} }
if (unlikely(iommu->need_sync)) iommu_completion_wait(iommu);
iommu_completion_wait(iommu);
spin_unlock_irqrestore(&domain->lock, flags); spin_unlock_irqrestore(&domain->lock, flags);
} }
...@@ -1225,8 +1223,7 @@ static void *alloc_coherent(struct device *dev, size_t size, ...@@ -1225,8 +1223,7 @@ static void *alloc_coherent(struct device *dev, size_t size,
goto out; goto out;
} }
if (unlikely(iommu->need_sync)) iommu_completion_wait(iommu);
iommu_completion_wait(iommu);
out: out:
spin_unlock_irqrestore(&domain->lock, flags); spin_unlock_irqrestore(&domain->lock, flags);
...@@ -1257,8 +1254,7 @@ static void free_coherent(struct device *dev, size_t size, ...@@ -1257,8 +1254,7 @@ static void free_coherent(struct device *dev, size_t size,
__unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
if (unlikely(iommu->need_sync)) iommu_completion_wait(iommu);
iommu_completion_wait(iommu);
spin_unlock_irqrestore(&domain->lock, flags); spin_unlock_irqrestore(&domain->lock, flags);
......
...@@ -604,6 +604,9 @@ static void __init __get_smp_config(unsigned int early) ...@@ -604,6 +604,9 @@ static void __init __get_smp_config(unsigned int early)
printk(KERN_INFO "Using ACPI for processor (LAPIC) " printk(KERN_INFO "Using ACPI for processor (LAPIC) "
"configuration information\n"); "configuration information\n");
if (!mpf)
return;
printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
mpf->mpf_specification); mpf->mpf_specification);
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
......
...@@ -123,6 +123,8 @@ static void free_iommu(unsigned long offset, int size) ...@@ -123,6 +123,8 @@ static void free_iommu(unsigned long offset, int size)
spin_lock_irqsave(&iommu_bitmap_lock, flags); spin_lock_irqsave(&iommu_bitmap_lock, flags);
iommu_area_free(iommu_gart_bitmap, offset, size); iommu_area_free(iommu_gart_bitmap, offset, size);
if (offset >= next_bit)
next_bit = offset + size;
spin_unlock_irqrestore(&iommu_bitmap_lock, flags); spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
} }
......
...@@ -401,14 +401,13 @@ static int __init ppro_init(char **cpu_type) ...@@ -401,14 +401,13 @@ static int __init ppro_init(char **cpu_type)
*cpu_type = "i386/pii"; *cpu_type = "i386/pii";
break; break;
case 6 ... 8: case 6 ... 8:
case 10 ... 11:
*cpu_type = "i386/piii"; *cpu_type = "i386/piii";
break; break;
case 9: case 9:
case 13:
*cpu_type = "i386/p6_mobile"; *cpu_type = "i386/p6_mobile";
break; break;
case 10 ... 13:
*cpu_type = "i386/p6";
break;
case 14: case 14:
*cpu_type = "i386/core"; *cpu_type = "i386/core";
break; break;
......
...@@ -156,6 +156,8 @@ static void ppro_start(struct op_msrs const * const msrs) ...@@ -156,6 +156,8 @@ static void ppro_start(struct op_msrs const * const msrs)
unsigned int low, high; unsigned int low, high;
int i; int i;
if (!reset_value)
return;
for (i = 0; i < num_counters; ++i) { for (i = 0; i < num_counters; ++i) {
if (reset_value[i]) { if (reset_value[i]) {
CTRL_READ(low, high, msrs, i); CTRL_READ(low, high, msrs, i);
...@@ -171,6 +173,8 @@ static void ppro_stop(struct op_msrs const * const msrs) ...@@ -171,6 +173,8 @@ static void ppro_stop(struct op_msrs const * const msrs)
unsigned int low, high; unsigned int low, high;
int i; int i;
if (!reset_value)
return;
for (i = 0; i < num_counters; ++i) { for (i = 0; i < num_counters; ++i) {
if (!reset_value[i]) if (!reset_value[i])
continue; continue;
......
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