Commit e98d5023 authored by Masahiro Yamada's avatar Masahiro Yamada

arm64: dts: uniphier: add reset-names to NAND controller node

The Denali NAND controller IP has separate reset control for the
controller core and registers.

Add the reset-names, and one more phandle accordingly. This is the
approved DT-binding.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent e42617b8
...@@ -633,7 +633,8 @@ nand: nand@68000000 { ...@@ -633,7 +633,8 @@ nand: nand@68000000 {
pinctrl-0 = <&pinctrl_nand>; pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc"; clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>; reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
}; };
}; };
}; };
......
...@@ -937,7 +937,8 @@ nand: nand@68000000 { ...@@ -937,7 +937,8 @@ nand: nand@68000000 {
pinctrl-0 = <&pinctrl_nand>; pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc"; clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>; reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
}; };
}; };
}; };
......
...@@ -795,7 +795,8 @@ nand: nand@68000000 { ...@@ -795,7 +795,8 @@ nand: nand@68000000 {
pinctrl-0 = <&pinctrl_nand>; pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc"; clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>; reset-names = "nand", "reg";
resets = <&sys_rst 2>, <&sys_rst 2>;
}; };
}; };
}; };
......
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